git.sur5r.net Git - u-boot/blob - drivers/pwm/rk_pwm.c

   1 /*
   2  * Copyright (c) 2016 Google, Inc
   3  * Written by Simon Glass <sjg@chromium.org>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <div64.h>
  11 #include <dm.h>
  12 #include <pwm.h>
  13 #include <regmap.h>
  14 #include <syscon.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/pwm.h>
  17 #include <power/regulator.h>
  18
  19 struct rk_pwm_priv {
  20         struct rk3288_pwm *regs;
  21         ulong freq;
  22         uint enable_conf;
  23 };
  24
  25 static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
  26 {
  27         struct rk_pwm_priv *priv = dev_get_priv(dev);
  28
  29         debug("%s: polarity=%u\n", __func__, polarity);
  30         priv->enable_conf &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
  31         if (polarity)
  32                 priv->enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
  33         else
  34                 priv->enable_conf |= PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
  35
  36         return 0;
  37 }
  38
  39 static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
  40                              uint duty_ns)
  41 {
  42         struct rk_pwm_priv *priv = dev_get_priv(dev);
  43         struct rk3288_pwm *regs = priv->regs;
  44         unsigned long period, duty;
  45
  46         debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
  47         writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
  48                 PWM_CONTINUOUS | priv->enable_conf |
  49                 RK_PWM_DISABLE,
  50                 &regs->ctrl);
  51
  52         period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 1000000);
  53         duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 1000000);
  54
  55         writel(period, &regs->period_hpr);
  56         writel(duty, &regs->duty_lpr);
  57         debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
  58
  59         return 0;
  60 }
  61
  62 static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
  63 {
  64         struct rk_pwm_priv *priv = dev_get_priv(dev);
  65         struct rk3288_pwm *regs = priv->regs;
  66
  67         debug("%s: Enable '%s'\n", __func__, dev->name);
  68         clrsetbits_le32(&regs->ctrl, RK_PWM_ENABLE, enable ? RK_PWM_ENABLE : 0);
  69
  70         return 0;
  71 }
  72
  73 static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
  74 {
  75         struct rk_pwm_priv *priv = dev_get_priv(dev);
  76
  77         priv->regs = (struct rk3288_pwm *)dev_read_addr(dev);
  78
  79         return 0;
  80 }
  81
  82 static int rk_pwm_probe(struct udevice *dev)
  83 {
  84         struct rk_pwm_priv *priv = dev_get_priv(dev);
  85         struct clk clk;
  86         int ret = 0;
  87
  88         ret = clk_get_by_index(dev, 0, &clk);
  89         if (ret < 0) {
  90                 debug("%s get clock fail!\n", __func__);
  91                 return -EINVAL;
  92         }
  93         priv->freq = clk_get_rate(&clk);
  94         priv->enable_conf = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE;
  95
  96         return 0;
  97 }
  98
  99 static const struct pwm_ops rk_pwm_ops = {
 100         .set_invert     = rk_pwm_set_invert,
 101         .set_config     = rk_pwm_set_config,
 102         .set_enable     = rk_pwm_set_enable,
 103 };
 104
 105 static const struct udevice_id rk_pwm_ids[] = {
 106         { .compatible = "rockchip,rk3288-pwm" },
 107         { }
 108 };
 109
 110 U_BOOT_DRIVER(rk_pwm) = {
 111         .name   = "rk_pwm",
 112         .id     = UCLASS_PWM,
 113         .of_match = rk_pwm_ids,
 114         .ops    = &rk_pwm_ops,
 115         .ofdata_to_platdata     = rk_pwm_ofdata_to_platdata,
 116         .probe          = rk_pwm_probe,
 117         .priv_auto_alloc_size   = sizeof(struct rk_pwm_priv),
 118 };