2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include "asm/errno.h"
27 #include "asm/immap_qe.h"
33 #if defined(CONFIG_QE)
35 #ifdef CONFIG_UEC_ETH1
36 static uec_info_t eth1_uec_info = {
38 .ucc_num = CFG_UEC1_UCC_NUM,
39 .rx_clock = CFG_UEC1_RX_CLK,
40 .tx_clock = CFG_UEC1_TX_CLK,
41 .eth_type = CFG_UEC1_ETH_TYPE,
43 #if (CFG_UEC1_ETH_TYPE == FAST_ETH)
44 .num_threads_tx = UEC_NUM_OF_THREADS_1,
45 .num_threads_rx = UEC_NUM_OF_THREADS_1,
47 .num_threads_tx = UEC_NUM_OF_THREADS_4,
48 .num_threads_rx = UEC_NUM_OF_THREADS_4,
50 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
51 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
54 .phy_address = CFG_UEC1_PHY_ADDR,
55 .enet_interface = CFG_UEC1_INTERFACE_MODE,
58 #ifdef CONFIG_UEC_ETH2
59 static uec_info_t eth2_uec_info = {
61 .ucc_num = CFG_UEC2_UCC_NUM,
62 .rx_clock = CFG_UEC2_RX_CLK,
63 .tx_clock = CFG_UEC2_TX_CLK,
64 .eth_type = CFG_UEC2_ETH_TYPE,
66 #if (CFG_UEC2_ETH_TYPE == FAST_ETH)
67 .num_threads_tx = UEC_NUM_OF_THREADS_1,
68 .num_threads_rx = UEC_NUM_OF_THREADS_1,
70 .num_threads_tx = UEC_NUM_OF_THREADS_4,
71 .num_threads_rx = UEC_NUM_OF_THREADS_4,
73 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
74 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
77 .phy_address = CFG_UEC2_PHY_ADDR,
78 .enet_interface = CFG_UEC2_INTERFACE_MODE,
81 #ifdef CONFIG_UEC_ETH3
82 static uec_info_t eth3_uec_info = {
84 .ucc_num = CFG_UEC3_UCC_NUM,
85 .rx_clock = CFG_UEC3_RX_CLK,
86 .tx_clock = CFG_UEC3_TX_CLK,
87 .eth_type = CFG_UEC3_ETH_TYPE,
89 #if (CFG_UEC3_ETH_TYPE == FAST_ETH)
90 .num_threads_tx = UEC_NUM_OF_THREADS_1,
91 .num_threads_rx = UEC_NUM_OF_THREADS_1,
93 .num_threads_tx = UEC_NUM_OF_THREADS_4,
94 .num_threads_rx = UEC_NUM_OF_THREADS_4,
96 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
97 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
100 .phy_address = CFG_UEC3_PHY_ADDR,
101 .enet_interface = CFG_UEC3_INTERFACE_MODE,
104 #ifdef CONFIG_UEC_ETH4
105 static uec_info_t eth4_uec_info = {
107 .ucc_num = CFG_UEC4_UCC_NUM,
108 .rx_clock = CFG_UEC4_RX_CLK,
109 .tx_clock = CFG_UEC4_TX_CLK,
110 .eth_type = CFG_UEC4_ETH_TYPE,
112 #if (CFG_UEC4_ETH_TYPE == FAST_ETH)
113 .num_threads_tx = UEC_NUM_OF_THREADS_1,
114 .num_threads_rx = UEC_NUM_OF_THREADS_1,
116 .num_threads_tx = UEC_NUM_OF_THREADS_4,
117 .num_threads_rx = UEC_NUM_OF_THREADS_4,
119 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
120 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
121 .tx_bd_ring_len = 16,
122 .rx_bd_ring_len = 16,
123 .phy_address = CFG_UEC4_PHY_ADDR,
124 .enet_interface = CFG_UEC4_INTERFACE_MODE,
128 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
134 printf("%s: uec not initial\n", __FUNCTION__);
137 uec_regs = uec->uec_regs;
139 maccfg1 = in_be32(&uec_regs->maccfg1);
141 if (mode & COMM_DIR_TX) {
142 maccfg1 |= MACCFG1_ENABLE_TX;
143 out_be32(&uec_regs->maccfg1, maccfg1);
144 uec->mac_tx_enabled = 1;
147 if (mode & COMM_DIR_RX) {
148 maccfg1 |= MACCFG1_ENABLE_RX;
149 out_be32(&uec_regs->maccfg1, maccfg1);
150 uec->mac_rx_enabled = 1;
156 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
162 printf("%s: uec not initial\n", __FUNCTION__);
165 uec_regs = uec->uec_regs;
167 maccfg1 = in_be32(&uec_regs->maccfg1);
169 if (mode & COMM_DIR_TX) {
170 maccfg1 &= ~MACCFG1_ENABLE_TX;
171 out_be32(&uec_regs->maccfg1, maccfg1);
172 uec->mac_tx_enabled = 0;
175 if (mode & COMM_DIR_RX) {
176 maccfg1 &= ~MACCFG1_ENABLE_RX;
177 out_be32(&uec_regs->maccfg1, maccfg1);
178 uec->mac_rx_enabled = 0;
184 static int uec_graceful_stop_tx(uec_private_t *uec)
190 if (!uec || !uec->uccf) {
191 printf("%s: No handle passed.\n", __FUNCTION__);
195 uf_regs = uec->uccf->uf_regs;
197 /* Clear the grace stop event */
198 out_be32(&uf_regs->ucce, UCCE_GRA);
200 /* Issue host command */
202 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
203 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
204 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
206 /* Wait for command to complete */
208 ucce = in_be32(&uf_regs->ucce);
209 } while (! (ucce & UCCE_GRA));
211 uec->grace_stopped_tx = 1;
216 static int uec_graceful_stop_rx(uec_private_t *uec)
222 printf("%s: No handle passed.\n", __FUNCTION__);
226 if (!uec->p_rx_glbl_pram) {
227 printf("%s: No init rx global parameter\n", __FUNCTION__);
231 /* Clear acknowledge bit */
232 ack = uec->p_rx_glbl_pram->rxgstpack;
233 ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
234 uec->p_rx_glbl_pram->rxgstpack = ack;
236 /* Keep issuing cmd and checking ack bit until it is asserted */
238 /* Issue host command */
240 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
241 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
242 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
243 ack = uec->p_rx_glbl_pram->rxgstpack;
244 } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
246 uec->grace_stopped_rx = 1;
251 static int uec_restart_tx(uec_private_t *uec)
255 if (!uec || !uec->uec_info) {
256 printf("%s: No handle passed.\n", __FUNCTION__);
261 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
262 qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
263 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
265 uec->grace_stopped_tx = 0;
270 static int uec_restart_rx(uec_private_t *uec)
274 if (!uec || !uec->uec_info) {
275 printf("%s: No handle passed.\n", __FUNCTION__);
280 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
281 qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
282 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
284 uec->grace_stopped_rx = 0;
289 static int uec_open(uec_private_t *uec, comm_dir_e mode)
291 ucc_fast_private_t *uccf;
293 if (!uec || !uec->uccf) {
294 printf("%s: No handle passed.\n", __FUNCTION__);
299 /* check if the UCC number is in range. */
300 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
301 printf("%s: ucc_num out of range.\n", __FUNCTION__);
306 uec_mac_enable(uec, mode);
308 /* Enable UCC fast */
309 ucc_fast_enable(uccf, mode);
311 /* RISC microcode start */
312 if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
315 if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
322 static int uec_stop(uec_private_t *uec, comm_dir_e mode)
324 ucc_fast_private_t *uccf;
326 if (!uec || !uec->uccf) {
327 printf("%s: No handle passed.\n", __FUNCTION__);
332 /* check if the UCC number is in range. */
333 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
334 printf("%s: ucc_num out of range.\n", __FUNCTION__);
337 /* Stop any transmissions */
338 if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
339 uec_graceful_stop_tx(uec);
341 /* Stop any receptions */
342 if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
343 uec_graceful_stop_rx(uec);
346 /* Disable the UCC fast */
347 ucc_fast_disable(uec->uccf, mode);
349 /* Disable the MAC */
350 uec_mac_disable(uec, mode);
355 static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
361 printf("%s: uec not initial\n", __FUNCTION__);
364 uec_regs = uec->uec_regs;
366 if (duplex == DUPLEX_HALF) {
367 maccfg2 = in_be32(&uec_regs->maccfg2);
368 maccfg2 &= ~MACCFG2_FDX;
369 out_be32(&uec_regs->maccfg2, maccfg2);
372 if (duplex == DUPLEX_FULL) {
373 maccfg2 = in_be32(&uec_regs->maccfg2);
374 maccfg2 |= MACCFG2_FDX;
375 out_be32(&uec_regs->maccfg2, maccfg2);
381 static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
383 enet_interface_e enet_if_mode;
384 uec_info_t *uec_info;
390 printf("%s: uec not initial\n", __FUNCTION__);
394 uec_info = uec->uec_info;
395 uec_regs = uec->uec_regs;
396 enet_if_mode = if_mode;
398 maccfg2 = in_be32(&uec_regs->maccfg2);
399 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
401 upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
402 upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
404 switch (enet_if_mode) {
407 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
410 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
413 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
417 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
418 upsmr |= (UPSMR_RPM | UPSMR_TBIM);
420 case ENET_1000_RGMII_RXID:
421 case ENET_1000_RGMII:
422 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
426 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
430 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
431 upsmr |= (UPSMR_RPM | UPSMR_R10M);
434 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
438 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
439 upsmr |= (UPSMR_R10M | UPSMR_RMM);
445 out_be32(&uec_regs->maccfg2, maccfg2);
446 out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
451 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
453 uint timeout = 0x1000;
456 miimcfg = in_be32(&uec_mii_regs->miimcfg);
457 miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
458 out_be32(&uec_mii_regs->miimcfg, miimcfg);
460 /* Wait until the bus is free */
461 while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
463 printf("%s: The MII Bus is stuck!", __FUNCTION__);
470 static int init_phy(struct eth_device *dev)
473 uec_mii_t *umii_regs;
474 struct uec_mii_info *mii_info;
475 struct phy_info *curphy;
478 uec = (uec_private_t *)dev->priv;
479 umii_regs = uec->uec_mii_regs;
485 mii_info = malloc(sizeof(*mii_info));
487 printf("%s: Could not allocate mii_info", dev->name);
490 memset(mii_info, 0, sizeof(*mii_info));
492 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
493 mii_info->speed = SPEED_1000;
495 mii_info->speed = SPEED_100;
498 mii_info->duplex = DUPLEX_FULL;
502 mii_info->advertising = (ADVERTISED_10baseT_Half |
503 ADVERTISED_10baseT_Full |
504 ADVERTISED_100baseT_Half |
505 ADVERTISED_100baseT_Full |
506 ADVERTISED_1000baseT_Full);
507 mii_info->autoneg = 1;
508 mii_info->mii_id = uec->uec_info->phy_address;
511 mii_info->mdio_read = &uec_read_phy_reg;
512 mii_info->mdio_write = &uec_write_phy_reg;
514 uec->mii_info = mii_info;
516 qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
518 if (init_mii_management_configuration(umii_regs)) {
519 printf("%s: The MII Bus is stuck!", dev->name);
524 /* get info for this PHY */
525 curphy = uec_get_phy_info(uec->mii_info);
527 printf("%s: No PHY found", dev->name);
532 mii_info->phyinfo = curphy;
534 /* Run the commands which initialize the PHY */
536 err = curphy->init(uec->mii_info);
550 static void adjust_link(struct eth_device *dev)
552 uec_private_t *uec = (uec_private_t *)dev->priv;
554 struct uec_mii_info *mii_info = uec->mii_info;
556 extern void change_phy_interface_mode(struct eth_device *dev,
557 enet_interface_e mode);
558 uec_regs = uec->uec_regs;
560 if (mii_info->link) {
561 /* Now we make sure that we can be in full duplex mode.
562 * If not, we operate in half-duplex mode. */
563 if (mii_info->duplex != uec->oldduplex) {
564 if (!(mii_info->duplex)) {
565 uec_set_mac_duplex(uec, DUPLEX_HALF);
566 printf("%s: Half Duplex\n", dev->name);
568 uec_set_mac_duplex(uec, DUPLEX_FULL);
569 printf("%s: Full Duplex\n", dev->name);
571 uec->oldduplex = mii_info->duplex;
574 if (mii_info->speed != uec->oldspeed) {
575 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
576 switch (mii_info->speed) {
580 printf ("switching to rgmii 100\n");
581 /* change phy to rgmii 100 */
582 change_phy_interface_mode(dev,
584 /* change the MAC interface mode */
585 uec_set_mac_if_mode(uec,ENET_100_RGMII);
588 printf ("switching to rgmii 10\n");
589 /* change phy to rgmii 10 */
590 change_phy_interface_mode(dev,
592 /* change the MAC interface mode */
593 uec_set_mac_if_mode(uec,ENET_10_RGMII);
596 printf("%s: Ack,Speed(%d)is illegal\n",
597 dev->name, mii_info->speed);
602 printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
603 uec->oldspeed = mii_info->speed;
607 printf("%s: Link is up\n", dev->name);
611 } else { /* if (mii_info->link) */
613 printf("%s: Link is down\n", dev->name);
621 static void phy_change(struct eth_device *dev)
623 uec_private_t *uec = (uec_private_t *)dev->priv;
625 /* Update the link, speed, duplex */
626 uec->mii_info->phyinfo->read_status(uec->mii_info);
628 /* Adjust the interface according to speed */
632 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
639 printf("%s: uec not initial\n", __FUNCTION__);
643 uec_regs = uec->uec_regs;
645 /* if a station address of 0x12345678ABCD, perform a write to
646 MACSTNADDR1 of 0xCDAB7856,
647 MACSTNADDR2 of 0x34120000 */
649 mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
650 (mac_addr[3] << 8) | (mac_addr[2]);
651 out_be32(&uec_regs->macstnaddr1, mac_addr1);
653 mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
654 out_be32(&uec_regs->macstnaddr2, mac_addr2);
659 static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
660 int *threads_num_ret)
662 int num_threads_numerica;
664 switch (threads_num) {
665 case UEC_NUM_OF_THREADS_1:
666 num_threads_numerica = 1;
668 case UEC_NUM_OF_THREADS_2:
669 num_threads_numerica = 2;
671 case UEC_NUM_OF_THREADS_4:
672 num_threads_numerica = 4;
674 case UEC_NUM_OF_THREADS_6:
675 num_threads_numerica = 6;
677 case UEC_NUM_OF_THREADS_8:
678 num_threads_numerica = 8;
681 printf("%s: Bad number of threads value.",
686 *threads_num_ret = num_threads_numerica;
691 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
693 uec_info_t *uec_info;
698 uec_info = uec->uec_info;
700 /* Alloc global Tx parameter RAM page */
701 uec->tx_glbl_pram_offset = qe_muram_alloc(
702 sizeof(uec_tx_global_pram_t),
703 UEC_TX_GLOBAL_PRAM_ALIGNMENT);
704 uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
705 qe_muram_addr(uec->tx_glbl_pram_offset);
707 /* Zero the global Tx prameter RAM */
708 memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
710 /* Init global Tx parameter RAM */
712 /* TEMODER, RMON statistics disable, one Tx queue */
713 out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
716 uec->send_q_mem_reg_offset = qe_muram_alloc(
717 sizeof(uec_send_queue_qd_t),
718 UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
719 uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
720 qe_muram_addr(uec->send_q_mem_reg_offset);
721 out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
723 /* Setup the table with TxBDs ring */
724 end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
726 out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
727 (u32)(uec->p_tx_bd_ring));
728 out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
731 /* Scheduler Base Pointer, we have only one Tx queue, no need it */
732 out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
734 /* TxRMON Base Pointer, TxRMON disable, we don't need it */
735 out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
737 /* TSTATE, global snooping, big endian, the CSB bus selected */
738 bmrx = BMR_INIT_VALUE;
739 out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
742 for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
743 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
747 for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
748 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
752 uec->thread_dat_tx_offset = qe_muram_alloc(
753 num_threads_tx * sizeof(uec_thread_data_tx_t) +
754 32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
756 uec->p_thread_data_tx = (uec_thread_data_tx_t *)
757 qe_muram_addr(uec->thread_dat_tx_offset);
758 out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
761 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
765 uec_82xx_address_filtering_pram_t *p_af_pram;
767 /* Allocate global Rx parameter RAM page */
768 uec->rx_glbl_pram_offset = qe_muram_alloc(
769 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
770 uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
771 qe_muram_addr(uec->rx_glbl_pram_offset);
773 /* Zero Global Rx parameter RAM */
774 memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
776 /* Init global Rx parameter RAM */
777 /* REMODER, Extended feature mode disable, VLAN disable,
778 LossLess flow control disable, Receive firmware statisic disable,
779 Extended address parsing mode disable, One Rx queues,
780 Dynamic maximum/minimum frame length disable, IP checksum check
781 disable, IP address alignment disable
783 out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
786 uec->thread_dat_rx_offset = qe_muram_alloc(
787 num_threads_rx * sizeof(uec_thread_data_rx_t),
788 UEC_THREAD_DATA_ALIGNMENT);
789 uec->p_thread_data_rx = (uec_thread_data_rx_t *)
790 qe_muram_addr(uec->thread_dat_rx_offset);
791 out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
794 out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
796 /* RxRMON base pointer, we don't need it */
797 out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
799 /* IntCoalescingPTR, we don't need it, no interrupt */
800 out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
802 /* RSTATE, global snooping, big endian, the CSB bus selected */
803 bmrx = BMR_INIT_VALUE;
804 out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
807 out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
810 uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
811 sizeof(uec_rx_bd_queues_entry_t) + \
812 sizeof(uec_rx_prefetched_bds_t),
813 UEC_RX_BD_QUEUES_ALIGNMENT);
814 uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
815 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
818 memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
819 sizeof(uec_rx_prefetched_bds_t));
820 out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
821 out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
822 (u32)uec->p_rx_bd_ring);
825 out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
827 out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
829 out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
831 out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
833 out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
835 out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
837 for (i = 0; i < 8; i++) {
838 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
842 out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
844 out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
846 /* Clear PQ2 style address filtering hash table */
847 p_af_pram = (uec_82xx_address_filtering_pram_t *) \
848 uec->p_rx_glbl_pram->addressfiltering;
850 p_af_pram->iaddr_h = 0;
851 p_af_pram->iaddr_l = 0;
852 p_af_pram->gaddr_h = 0;
853 p_af_pram->gaddr_l = 0;
856 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
857 int thread_tx, int thread_rx)
859 uec_init_cmd_pram_t *p_init_enet_param;
860 u32 init_enet_param_offset;
861 uec_info_t *uec_info;
864 u32 init_enet_offset;
869 uec_info = uec->uec_info;
871 /* Allocate init enet command parameter */
872 uec->init_enet_param_offset = qe_muram_alloc(
873 sizeof(uec_init_cmd_pram_t), 4);
874 init_enet_param_offset = uec->init_enet_param_offset;
875 uec->p_init_enet_param = (uec_init_cmd_pram_t *)
876 qe_muram_addr(uec->init_enet_param_offset);
878 /* Zero init enet command struct */
879 memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
881 /* Init the command struct */
882 p_init_enet_param = uec->p_init_enet_param;
883 p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
884 p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
885 p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
886 p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
887 p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
888 p_init_enet_param->largestexternallookupkeysize = 0;
890 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
891 << ENET_INIT_PARAM_RGF_SHIFT;
892 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
893 << ENET_INIT_PARAM_TGF_SHIFT;
895 /* Init Rx global parameter pointer */
896 p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
897 (u32)uec_info->riscRx;
899 /* Init Rx threads */
900 for (i = 0; i < (thread_rx + 1); i++) {
901 if ((snum = qe_get_snum()) < 0) {
902 printf("%s can not get snum\n", __FUNCTION__);
907 init_enet_offset = 0;
909 init_enet_offset = qe_muram_alloc(
910 sizeof(uec_thread_rx_pram_t),
911 UEC_THREAD_RX_PRAM_ALIGNMENT);
914 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
915 init_enet_offset | (u32)uec_info->riscRx;
916 p_init_enet_param->rxthread[i] = entry_val;
919 /* Init Tx global parameter pointer */
920 p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
921 (u32)uec_info->riscTx;
923 /* Init Tx threads */
924 for (i = 0; i < thread_tx; i++) {
925 if ((snum = qe_get_snum()) < 0) {
926 printf("%s can not get snum\n", __FUNCTION__);
930 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
931 UEC_THREAD_TX_PRAM_ALIGNMENT);
933 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
934 init_enet_offset | (u32)uec_info->riscTx;
935 p_init_enet_param->txthread[i] = entry_val;
938 __asm__ __volatile__("sync");
940 /* Issue QE command */
941 command = QE_INIT_TX_RX;
942 cecr_subblock = ucc_fast_get_qe_cr_subblock(
943 uec->uec_info->uf_info.ucc_num);
944 qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
945 init_enet_param_offset);
950 static int uec_startup(uec_private_t *uec)
952 uec_info_t *uec_info;
953 ucc_fast_info_t *uf_info;
954 ucc_fast_private_t *uccf;
960 enet_interface_e enet_interface;
967 if (!uec || !uec->uec_info) {
968 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
972 uec_info = uec->uec_info;
973 uf_info = &(uec_info->uf_info);
975 /* Check if Rx BD ring len is illegal */
976 if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
977 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
978 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
983 /* Check if Tx BD ring len is illegal */
984 if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
985 printf("%s: Tx BD ring length must not be smaller than 2.\n",
990 /* Check if MRBLR is illegal */
991 if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT)) {
992 printf("%s: max rx buffer length must be mutliple of 128.\n",
997 /* Both Rx and Tx are stopped */
998 uec->grace_stopped_rx = 1;
999 uec->grace_stopped_tx = 1;
1002 if (ucc_fast_init(uf_info, &uccf)) {
1003 printf("%s: failed to init ucc fast\n", __FUNCTION__);
1010 /* Convert the Tx threads number */
1011 if (uec_convert_threads_num(uec_info->num_threads_tx,
1016 /* Convert the Rx threads number */
1017 if (uec_convert_threads_num(uec_info->num_threads_rx,
1022 uf_regs = uccf->uf_regs;
1024 /* UEC register is following UCC fast registers */
1025 uec_regs = (uec_t *)(&uf_regs->ucc_eth);
1027 /* Save the UEC register pointer to UEC private struct */
1028 uec->uec_regs = uec_regs;
1030 /* Init UPSMR, enable hardware statistics (UCC) */
1031 out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1033 /* Init MACCFG1, flow control disable, disable Tx and Rx */
1034 out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1036 /* Init MACCFG2, length check, MAC PAD and CRC enable */
1037 out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1039 /* Setup MAC interface mode */
1040 uec_set_mac_if_mode(uec, uec_info->enet_interface);
1042 /* Setup MII management base */
1043 #ifndef CONFIG_eTSEC_MDIO_BUS
1044 uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1046 uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
1049 /* Setup MII master clock source */
1050 qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1053 utbipar = in_be32(&uec_regs->utbipar);
1054 utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1055 enet_interface = uec->uec_info->enet_interface;
1056 if (enet_interface == ENET_1000_TBI ||
1057 enet_interface == ENET_1000_RTBI) {
1058 utbipar |= (uec_info->phy_address + uec_info->uf_info.ucc_num)
1059 << UTBIPAR_PHY_ADDRESS_SHIFT;
1061 utbipar |= (0x10 + uec_info->uf_info.ucc_num)
1062 << UTBIPAR_PHY_ADDRESS_SHIFT;
1065 out_be32(&uec_regs->utbipar, utbipar);
1067 /* Allocate Tx BDs */
1068 length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1069 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1070 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1071 if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1072 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1073 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1076 align = UEC_TX_BD_RING_ALIGNMENT;
1077 uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1078 if (uec->tx_bd_ring_offset != 0) {
1079 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1083 /* Zero all of Tx BDs */
1084 memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1086 /* Allocate Rx BDs */
1087 length = uec_info->rx_bd_ring_len * SIZEOFBD;
1088 align = UEC_RX_BD_RING_ALIGNMENT;
1089 uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1090 if (uec->rx_bd_ring_offset != 0) {
1091 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1095 /* Zero all of Rx BDs */
1096 memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1098 /* Allocate Rx buffer */
1099 length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1100 align = UEC_RX_DATA_BUF_ALIGNMENT;
1101 uec->rx_buf_offset = (u32)malloc(length + align);
1102 if (uec->rx_buf_offset != 0) {
1103 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1107 /* Zero all of the Rx buffer */
1108 memset((void *)(uec->rx_buf_offset), 0, length + align);
1110 /* Init TxBD ring */
1111 bd = (qe_bd_t *)uec->p_tx_bd_ring;
1114 for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1116 BD_STATUS_SET(bd, 0);
1117 BD_LENGTH_SET(bd, 0);
1120 BD_STATUS_SET((--bd), TxBD_WRAP);
1122 /* Init RxBD ring */
1123 bd = (qe_bd_t *)uec->p_rx_bd_ring;
1125 buf = uec->p_rx_buf;
1126 for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1127 BD_DATA_SET(bd, buf);
1128 BD_LENGTH_SET(bd, 0);
1129 BD_STATUS_SET(bd, RxBD_EMPTY);
1130 buf += MAX_RXBUF_LEN;
1133 BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1135 /* Init global Tx parameter RAM */
1136 uec_init_tx_parameter(uec, num_threads_tx);
1138 /* Init global Rx parameter RAM */
1139 uec_init_rx_parameter(uec, num_threads_rx);
1141 /* Init ethernet Tx and Rx parameter command */
1142 if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1144 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1151 static int uec_init(struct eth_device* dev, bd_t *bd)
1155 struct phy_info *curphy;
1157 uec = (uec_private_t *)dev->priv;
1159 if (uec->the_first_run == 0) {
1160 err = init_phy(dev);
1162 printf("%s: Cannot initialize PHY, aborting.\n",
1167 curphy = uec->mii_info->phyinfo;
1169 if (curphy->config_aneg) {
1170 err = curphy->config_aneg(uec->mii_info);
1172 printf("%s: Can't negotiate PHY\n", dev->name);
1177 /* Give PHYs up to 5 sec to report a link */
1180 err = curphy->read_status(uec->mii_info);
1182 } while (((i-- > 0) && !uec->mii_info->link) || err);
1185 printf("warning: %s: timeout on PHY link\n", dev->name);
1187 uec->the_first_run = 1;
1190 /* Set up the MAC address */
1191 if (dev->enetaddr[0] & 0x01) {
1192 printf("%s: MacAddress is multcast address\n",
1196 uec_set_mac_address(uec, dev->enetaddr);
1199 err = uec_open(uec, COMM_DIR_RX_AND_TX);
1201 printf("%s: cannot enable UEC device\n", dev->name);
1207 return (uec->mii_info->link ? 0 : -1);
1210 static void uec_halt(struct eth_device* dev)
1212 uec_private_t *uec = (uec_private_t *)dev->priv;
1213 uec_stop(uec, COMM_DIR_RX_AND_TX);
1216 static int uec_send(struct eth_device* dev, volatile void *buf, int len)
1219 ucc_fast_private_t *uccf;
1220 volatile qe_bd_t *bd;
1225 uec = (uec_private_t *)dev->priv;
1229 /* Find an empty TxBD */
1230 for (i = 0; bd->status & TxBD_READY; i++) {
1232 printf("%s: tx buffer not ready\n", dev->name);
1238 BD_DATA_SET(bd, buf);
1239 BD_LENGTH_SET(bd, len);
1240 status = bd->status;
1242 status |= (TxBD_READY | TxBD_LAST);
1243 BD_STATUS_SET(bd, status);
1245 /* Tell UCC to transmit the buffer */
1246 ucc_fast_transmit_on_demand(uccf);
1248 /* Wait for buffer to be transmitted */
1249 for (i = 0; bd->status & TxBD_READY; i++) {
1251 printf("%s: tx error\n", dev->name);
1256 /* Ok, the buffer be transimitted */
1257 BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1264 static int uec_recv(struct eth_device* dev)
1266 uec_private_t *uec = dev->priv;
1267 volatile qe_bd_t *bd;
1273 status = bd->status;
1275 while (!(status & RxBD_EMPTY)) {
1276 if (!(status & RxBD_ERROR)) {
1278 len = BD_LENGTH(bd);
1279 NetReceive(data, len);
1281 printf("%s: Rx error\n", dev->name);
1284 BD_LENGTH_SET(bd, 0);
1285 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1286 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
1287 status = bd->status;
1294 int uec_initialize(int index)
1296 struct eth_device *dev;
1299 uec_info_t *uec_info;
1302 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1305 memset(dev, 0, sizeof(struct eth_device));
1307 /* Allocate the UEC private struct */
1308 uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1312 memset(uec, 0, sizeof(uec_private_t));
1314 /* Init UEC private struct, they come from board.h */
1317 #ifdef CONFIG_UEC_ETH1
1318 uec_info = ð1_uec_info;
1320 } else if (index == 1) {
1321 #ifdef CONFIG_UEC_ETH2
1322 uec_info = ð2_uec_info;
1324 } else if (index == 2) {
1325 #ifdef CONFIG_UEC_ETH3
1326 uec_info = ð3_uec_info;
1328 } else if (index == 3) {
1329 #ifdef CONFIG_UEC_ETH4
1330 uec_info = ð4_uec_info;
1333 printf("%s: index is illegal.\n", __FUNCTION__);
1337 uec->uec_info = uec_info;
1339 sprintf(dev->name, "FSL UEC%d", index);
1341 dev->priv = (void *)uec;
1342 dev->init = uec_init;
1343 dev->halt = uec_halt;
1344 dev->send = uec_send;
1345 dev->recv = uec_recv;
1347 /* Clear the ethnet address */
1348 for (i = 0; i < 6; i++)
1349 dev->enetaddr[i] = 0;
1353 err = uec_startup(uec);
1355 printf("%s: Cannot configure net device, aborting.",dev->name);
1361 #endif /* CONFIG_QE */