2 * Copyright (C) 2005 Freescale Semiconductor, Inc.
4 * Author: Shlomi Gridish
6 * Description: UCC GETH Driver -- PHY handling
8 * Based on 8260_io/fcc_enet.c
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
20 #include "asm/errno.h"
21 #include "asm/immap_qe.h"
29 #define ugphy_printk(format, arg...) \
30 printf(format "\n", ## arg)
32 #define ugphy_dbg(format, arg...) \
33 ugphy_printk(format , ## arg)
34 #define ugphy_err(format, arg...) \
35 ugphy_printk(format , ## arg)
36 #define ugphy_info(format, arg...) \
37 ugphy_printk(format , ## arg)
38 #define ugphy_warn(format, arg...) \
39 ugphy_printk(format , ## arg)
41 #ifdef UEC_VERBOSE_DEBUG
42 #define ugphy_vdbg ugphy_dbg
44 #define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
45 #endif /* UEC_VERBOSE_DEBUG */
47 static void config_genmii_advert (struct uec_mii_info *mii_info);
48 static void genmii_setup_forced (struct uec_mii_info *mii_info);
49 static void genmii_restart_aneg (struct uec_mii_info *mii_info);
50 static int gbit_config_aneg (struct uec_mii_info *mii_info);
51 static int genmii_config_aneg (struct uec_mii_info *mii_info);
52 static int genmii_update_link (struct uec_mii_info *mii_info);
53 static int genmii_read_status (struct uec_mii_info *mii_info);
54 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
55 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
57 /* Write value to the PHY for this device to the register at regnum, */
58 /* waiting until the write is done before it returns. All PHY */
59 /* configuration has to be done through the TSEC1 MIIM regs */
60 void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
62 uec_private_t *ugeth = (uec_private_t *) dev->priv;
64 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
67 ug_regs = ugeth->uec_mii_regs;
69 /* Stop the MII management read cycle */
70 out_be32 (&ug_regs->miimcom, 0);
71 /* Setting up the MII Mangement Address Register */
72 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
73 out_be32 (&ug_regs->miimadd, tmp_reg);
75 /* Setting up the MII Mangement Control Register with the value */
76 out_be32 (&ug_regs->miimcon, (u32) value);
79 /* Wait till MII management write is complete */
80 while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY);
83 /* Reads from register regnum in the PHY for device dev, */
84 /* returning the value. Clears miimcom first. All PHY */
85 /* configuration has to be done through the TSEC1 MIIM regs */
86 int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
88 uec_private_t *ugeth = (uec_private_t *) dev->priv;
90 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
94 ug_regs = ugeth->uec_mii_regs;
96 /* Setting up the MII Mangement Address Register */
97 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
98 out_be32 (&ug_regs->miimadd, tmp_reg);
100 /* clear MII management command cycle */
101 out_be32 (&ug_regs->miimcom, 0);
104 /* Perform an MII management read cycle */
105 out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
107 /* Wait till MII management write is complete */
108 while ((in_be32 (&ug_regs->miimind)) &
109 (MIIMIND_NOT_VALID | MIIMIND_BUSY));
111 /* Read MII management status */
112 value = (u16) in_be32 (&ug_regs->miimstat);
115 ("read wrong value : mii_id %d,mii_reg %d, base %08x",
116 mii_id, mii_reg, (u32) & (ug_regs->miimcfg));
121 void mii_clear_phy_interrupt (struct uec_mii_info *mii_info)
123 if (mii_info->phyinfo->ack_interrupt)
124 mii_info->phyinfo->ack_interrupt (mii_info);
127 void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
130 mii_info->interrupts = interrupts;
131 if (mii_info->phyinfo->config_intr)
132 mii_info->phyinfo->config_intr (mii_info);
135 /* Writes MII_ADVERTISE with the appropriate values, after
136 * sanitizing advertise to make sure only supported features
139 static void config_genmii_advert (struct uec_mii_info *mii_info)
144 /* Only allow advertising what this PHY supports */
145 mii_info->advertising &= mii_info->phyinfo->features;
146 advertise = mii_info->advertising;
148 /* Setup standard advertisement */
149 adv = phy_read (mii_info, PHY_ANAR);
150 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
151 if (advertise & ADVERTISED_10baseT_Half)
152 adv |= ADVERTISE_10HALF;
153 if (advertise & ADVERTISED_10baseT_Full)
154 adv |= ADVERTISE_10FULL;
155 if (advertise & ADVERTISED_100baseT_Half)
156 adv |= ADVERTISE_100HALF;
157 if (advertise & ADVERTISED_100baseT_Full)
158 adv |= ADVERTISE_100FULL;
159 phy_write (mii_info, PHY_ANAR, adv);
162 static void genmii_setup_forced (struct uec_mii_info *mii_info)
165 u32 features = mii_info->phyinfo->features;
167 ctrl = phy_read (mii_info, PHY_BMCR);
169 ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS |
170 PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON);
171 ctrl |= PHY_BMCR_RESET;
173 switch (mii_info->speed) {
175 if (features & (SUPPORTED_1000baseT_Half
176 | SUPPORTED_1000baseT_Full)) {
177 ctrl |= PHY_BMCR_1000_MBPS;
180 mii_info->speed = SPEED_100;
182 if (features & (SUPPORTED_100baseT_Half
183 | SUPPORTED_100baseT_Full)) {
184 ctrl |= PHY_BMCR_100_MBPS;
187 mii_info->speed = SPEED_10;
189 if (features & (SUPPORTED_10baseT_Half
190 | SUPPORTED_10baseT_Full))
192 default: /* Unsupported speed! */
193 ugphy_err ("%s: Bad speed!", mii_info->dev->name);
197 phy_write (mii_info, PHY_BMCR, ctrl);
200 /* Enable and Restart Autonegotiation */
201 static void genmii_restart_aneg (struct uec_mii_info *mii_info)
205 ctl = phy_read (mii_info, PHY_BMCR);
206 ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
207 phy_write (mii_info, PHY_BMCR, ctl);
210 static int gbit_config_aneg (struct uec_mii_info *mii_info)
215 if (mii_info->autoneg) {
216 /* Configure the ADVERTISE register */
217 config_genmii_advert (mii_info);
218 advertise = mii_info->advertising;
220 adv = phy_read (mii_info, MII_1000BASETCONTROL);
221 adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
222 MII_1000BASETCONTROL_HALFDUPLEXCAP);
223 if (advertise & SUPPORTED_1000baseT_Half)
224 adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
225 if (advertise & SUPPORTED_1000baseT_Full)
226 adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
227 phy_write (mii_info, MII_1000BASETCONTROL, adv);
229 /* Start/Restart aneg */
230 genmii_restart_aneg (mii_info);
232 genmii_setup_forced (mii_info);
237 static int marvell_config_aneg (struct uec_mii_info *mii_info)
239 /* The Marvell PHY has an errata which requires
240 * that certain registers get written in order
241 * to restart autonegotiation */
242 phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET);
244 phy_write (mii_info, 0x1d, 0x1f);
245 phy_write (mii_info, 0x1e, 0x200c);
246 phy_write (mii_info, 0x1d, 0x5);
247 phy_write (mii_info, 0x1e, 0);
248 phy_write (mii_info, 0x1e, 0x100);
250 gbit_config_aneg (mii_info);
255 static int genmii_config_aneg (struct uec_mii_info *mii_info)
257 if (mii_info->autoneg) {
258 config_genmii_advert (mii_info);
259 genmii_restart_aneg (mii_info);
261 genmii_setup_forced (mii_info);
266 static int genmii_update_link (struct uec_mii_info *mii_info)
270 /* Status is read once to clear old link state */
271 phy_read (mii_info, PHY_BMSR);
274 * Wait if the link is up, and autonegotiation is in progress
275 * (ie - we're capable and it's not done)
277 status = phy_read(mii_info, PHY_BMSR);
278 if ((status & PHY_BMSR_LS) && (status & PHY_BMSR_AUTN_ABLE)
279 && !(status & PHY_BMSR_AUTN_COMP)) {
282 while (!(status & PHY_BMSR_AUTN_COMP)) {
286 if (i > UGETH_AN_TIMEOUT) {
292 udelay(1000); /* 1 ms */
293 status = phy_read(mii_info, PHY_BMSR);
296 udelay(500000); /* another 500 ms (results in faster booting) */
298 if (status & PHY_BMSR_LS)
307 static int genmii_read_status (struct uec_mii_info *mii_info)
312 /* Update the link, but return if there
314 err = genmii_update_link (mii_info);
318 if (mii_info->autoneg) {
319 status = phy_read(mii_info, MII_1000BASETSTATUS);
321 if (status & (LPA_1000FULL | LPA_1000HALF)) {
322 mii_info->speed = SPEED_1000;
323 if (status & LPA_1000FULL)
324 mii_info->duplex = DUPLEX_FULL;
326 mii_info->duplex = DUPLEX_HALF;
328 status = phy_read(mii_info, PHY_ANLPAR);
330 if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
331 mii_info->duplex = DUPLEX_FULL;
333 mii_info->duplex = DUPLEX_HALF;
334 if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
335 mii_info->speed = SPEED_100;
337 mii_info->speed = SPEED_10;
341 /* On non-aneg, we assume what we put in BMCR is the speed,
342 * though magic-aneg shouldn't prevent this case from occurring
348 static int bcm_init(struct uec_mii_info *mii_info)
350 struct eth_device *edev = mii_info->dev;
351 uec_private_t *uec = edev->priv;
353 gbit_config_aneg(mii_info);
355 if (uec->uec_info->enet_interface == ENET_1000_RGMII_RXID) {
359 /* Wait for aneg to complete. */
361 val = phy_read(mii_info, PHY_BMSR);
362 while (--cnt && !(val & PHY_BMSR_AUTN_COMP));
364 /* Set RDX clk delay. */
365 phy_write(mii_info, 0x18, 0x7 | (7 << 12));
367 val = phy_read(mii_info, 0x18);
368 /* Set RDX-RXC skew. */
370 val |= (7 | (7 << 12));
371 /* Write bits 14:0. */
373 phy_write(mii_info, 0x18, val);
379 static int marvell_init(struct uec_mii_info *mii_info)
381 struct eth_device *edev = mii_info->dev;
382 uec_private_t *uec = edev->priv;
384 if (uec->uec_info->enet_interface == ENET_1000_RGMII_ID) {
387 temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR);
388 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
389 phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);
391 temp = phy_read(mii_info, MII_M1111_PHY_EXT_SR);
392 temp &= ~MII_M1111_HWCFG_MODE_MASK;
393 temp |= MII_M1111_HWCFG_MODE_RGMII;
394 phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
396 phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET);
402 static int marvell_read_status (struct uec_mii_info *mii_info)
407 /* Update the link, but return if there
409 err = genmii_update_link (mii_info);
413 /* If the link is up, read the speed and duplex */
414 /* If we aren't autonegotiating, assume speeds
416 if (mii_info->autoneg && mii_info->link) {
419 status = phy_read (mii_info, MII_M1011_PHY_SPEC_STATUS);
421 /* Get the duplexity */
422 if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
423 mii_info->duplex = DUPLEX_FULL;
425 mii_info->duplex = DUPLEX_HALF;
428 speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
430 case MII_M1011_PHY_SPEC_STATUS_1000:
431 mii_info->speed = SPEED_1000;
433 case MII_M1011_PHY_SPEC_STATUS_100:
434 mii_info->speed = SPEED_100;
437 mii_info->speed = SPEED_10;
446 static int marvell_ack_interrupt (struct uec_mii_info *mii_info)
448 /* Clear the interrupts by reading the reg */
449 phy_read (mii_info, MII_M1011_IEVENT);
454 static int marvell_config_intr (struct uec_mii_info *mii_info)
456 if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
457 phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
459 phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
464 static int dm9161_init (struct uec_mii_info *mii_info)
467 phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) |
469 /* PHY and MAC connect */
470 phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) &
473 phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
475 config_genmii_advert (mii_info);
476 /* Start/restart aneg */
477 genmii_config_aneg (mii_info);
482 static int dm9161_config_aneg (struct uec_mii_info *mii_info)
487 static int dm9161_read_status (struct uec_mii_info *mii_info)
492 /* Update the link, but return if there was an error */
493 err = genmii_update_link (mii_info);
496 /* If the link is up, read the speed and duplex
497 If we aren't autonegotiating assume speeds are as set */
498 if (mii_info->autoneg && mii_info->link) {
499 status = phy_read (mii_info, MII_DM9161_SCSR);
500 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
501 mii_info->speed = SPEED_100;
503 mii_info->speed = SPEED_10;
505 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
506 mii_info->duplex = DUPLEX_FULL;
508 mii_info->duplex = DUPLEX_HALF;
514 static int dm9161_ack_interrupt (struct uec_mii_info *mii_info)
516 /* Clear the interrupt by reading the reg */
517 phy_read (mii_info, MII_DM9161_INTR);
522 static int dm9161_config_intr (struct uec_mii_info *mii_info)
524 if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
525 phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
527 phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
532 static void dm9161_close (struct uec_mii_info *mii_info)
536 static struct phy_info phy_info_dm9161 = {
537 .phy_id = 0x0181b880,
538 .phy_id_mask = 0x0ffffff0,
539 .name = "Davicom DM9161E",
541 .config_aneg = dm9161_config_aneg,
542 .read_status = dm9161_read_status,
543 .close = dm9161_close,
546 static struct phy_info phy_info_dm9161a = {
547 .phy_id = 0x0181b8a0,
548 .phy_id_mask = 0x0ffffff0,
549 .name = "Davicom DM9161A",
550 .features = MII_BASIC_FEATURES,
552 .config_aneg = dm9161_config_aneg,
553 .read_status = dm9161_read_status,
554 .ack_interrupt = dm9161_ack_interrupt,
555 .config_intr = dm9161_config_intr,
556 .close = dm9161_close,
559 static struct phy_info phy_info_marvell = {
560 .phy_id = 0x01410c00,
561 .phy_id_mask = 0xffffff00,
562 .name = "Marvell 88E11x1",
563 .features = MII_GBIT_FEATURES,
564 .init = &marvell_init,
565 .config_aneg = &marvell_config_aneg,
566 .read_status = &marvell_read_status,
567 .ack_interrupt = &marvell_ack_interrupt,
568 .config_intr = &marvell_config_intr,
571 static struct phy_info phy_info_bcm5481 = {
572 .phy_id = 0x0143bca0,
573 .phy_id_mask = 0xffffff0,
574 .name = "Broadcom 5481",
575 .features = MII_GBIT_FEATURES,
576 .read_status = genmii_read_status,
580 static struct phy_info phy_info_genmii = {
581 .phy_id = 0x00000000,
582 .phy_id_mask = 0x00000000,
583 .name = "Generic MII",
584 .features = MII_BASIC_FEATURES,
585 .config_aneg = genmii_config_aneg,
586 .read_status = genmii_read_status,
589 static struct phy_info *phy_info[] = {
598 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum)
600 return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum);
603 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val)
605 mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val);
608 /* Use the PHY ID registers to determine what type of PHY is attached
609 * to device dev. return a struct phy_info structure describing that PHY
611 struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
616 struct phy_info *theInfo = NULL;
618 /* Grab the bits from PHYIR1, and put them in the upper half */
619 phy_reg = phy_read (mii_info, PHY_PHYIDR1);
620 phy_ID = (phy_reg & 0xffff) << 16;
622 /* Grab the bits from PHYIR2, and put them in the lower half */
623 phy_reg = phy_read (mii_info, PHY_PHYIDR2);
624 phy_ID |= (phy_reg & 0xffff);
626 /* loop through all the known PHY types, and find one that */
627 /* matches the ID we read from the PHY. */
628 for (i = 0; phy_info[i]; i++)
629 if (phy_info[i]->phy_id ==
630 (phy_ID & phy_info[i]->phy_id_mask)) {
631 theInfo = phy_info[i];
635 /* This shouldn't happen, as we have generic PHY support */
636 if (theInfo == NULL) {
637 ugphy_info ("UEC: PHY id %x is not supported!", phy_ID);
640 ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID);
646 void marvell_phy_interface_mode (struct eth_device *dev,
647 enet_interface_e mode)
649 uec_private_t *uec = (uec_private_t *) dev->priv;
650 struct uec_mii_info *mii_info;
653 if (!uec->mii_info) {
654 printf ("%s: the PHY not initialized\n", __FUNCTION__);
657 mii_info = uec->mii_info;
659 if (mode == ENET_100_RGMII) {
660 phy_write (mii_info, 0x00, 0x9140);
661 phy_write (mii_info, 0x1d, 0x001f);
662 phy_write (mii_info, 0x1e, 0x200c);
663 phy_write (mii_info, 0x1d, 0x0005);
664 phy_write (mii_info, 0x1e, 0x0000);
665 phy_write (mii_info, 0x1e, 0x0100);
666 phy_write (mii_info, 0x09, 0x0e00);
667 phy_write (mii_info, 0x04, 0x01e1);
668 phy_write (mii_info, 0x00, 0x9140);
669 phy_write (mii_info, 0x00, 0x1000);
671 phy_write (mii_info, 0x00, 0x2900);
672 phy_write (mii_info, 0x14, 0x0cd2);
673 phy_write (mii_info, 0x00, 0xa100);
674 phy_write (mii_info, 0x09, 0x0000);
675 phy_write (mii_info, 0x1b, 0x800b);
676 phy_write (mii_info, 0x04, 0x05e1);
677 phy_write (mii_info, 0x00, 0xa100);
678 phy_write (mii_info, 0x00, 0x2100);
680 } else if (mode == ENET_10_RGMII) {
681 phy_write (mii_info, 0x14, 0x8e40);
682 phy_write (mii_info, 0x1b, 0x800b);
683 phy_write (mii_info, 0x14, 0x0c82);
684 phy_write (mii_info, 0x00, 0x8100);
688 /* handle 88e1111 rev.B2 erratum 5.6 */
689 if (mii_info->autoneg) {
690 status = phy_read (mii_info, PHY_BMCR);
691 phy_write (mii_info, PHY_BMCR, status | PHY_BMCR_AUTON);
693 /* now the B2 will correctly report autoneg completion status */
696 void change_phy_interface_mode (struct eth_device *dev, enet_interface_e mode)
698 #ifdef CONFIG_PHY_MODE_NEED_CHANGE
699 marvell_phy_interface_mode (dev, mode);