git.sur5r.net Git - u-boot/blob - drivers/serial/serial_pl01x.c

   1 /*
   2  * (C) Copyright 2000
   3  * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
   4  *
   5  * (C) Copyright 2004
   6  * ARM Ltd.
   7  * Philippe Robin, <philippe.robin@arm.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
  13
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <watchdog.h>
  18 #include <asm/io.h>
  19 #include <serial.h>
  20 #include <dm/platform_data/serial_pl01x.h>
  21 #include <linux/compiler.h>
  22 #include "serial_pl01x_internal.h"
  23
  24 #ifndef CONFIG_DM_SERIAL
  25
  26 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
  27 static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
  28 static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
  29 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32 #endif
  33
  34 static int pl01x_putc(struct pl01x_regs *regs, char c)
  35 {
  36         /* Wait until there is space in the FIFO */
  37         if (readl(&regs->fr) & UART_PL01x_FR_TXFF)
  38                 return -EAGAIN;
  39
  40         /* Send the character */
  41         writel(c, &regs->dr);
  42
  43         return 0;
  44 }
  45
  46 static int pl01x_getc(struct pl01x_regs *regs)
  47 {
  48         unsigned int data;
  49
  50         /* Wait until there is data in the FIFO */
  51         if (readl(&regs->fr) & UART_PL01x_FR_RXFE)
  52                 return -EAGAIN;
  53
  54         data = readl(&regs->dr);
  55
  56         /* Check for an error flag */
  57         if (data & 0xFFFFFF00) {
  58                 /* Clear the error */
  59                 writel(0xFFFFFFFF, &regs->ecr);
  60                 return -1;
  61         }
  62
  63         return (int) data;
  64 }
  65
  66 static int pl01x_tstc(struct pl01x_regs *regs)
  67 {
  68         WATCHDOG_RESET();
  69         return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
  70 }
  71
  72 static int pl01x_generic_serial_init(struct pl01x_regs *regs,
  73                                      enum pl01x_type type)
  74 {
  75 #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
  76         if (type == TYPE_PL011) {
  77                 /* Empty RX fifo if necessary */
  78                 if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
  79                         while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
  80                                 readl(&regs->dr);
  81                 }
  82         }
  83 #endif
  84
  85         switch (type) {
  86         case TYPE_PL010:
  87                 /* disable everything */
  88                 writel(0, &regs->pl010_cr);
  89                 break;
  90         case TYPE_PL011:
  91                 /* disable everything */
  92                 writel(0, &regs->pl011_cr);
  93                 break;
  94         default:
  95                 return -EINVAL;
  96         }
  97
  98         return 0;
  99 }
 100
 101 static int set_line_control(struct pl01x_regs *regs)
 102 {
 103         unsigned int lcr;
 104         /*
 105          * Internal update of baud rate register require line
 106          * control register write
 107          */
 108         lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
 109 #ifdef CONFIG_PL011_SERIAL_RLCR
 110         {
 111                 int i;
 112
 113                 /*
 114                  * Program receive line control register after waiting
 115                  * 10 bus cycles.  Delay be writing to readonly register
 116                  * 10 times
 117                  */
 118                 for (i = 0; i < 10; i++)
 119                         writel(lcr, &regs->fr);
 120
 121                 writel(lcr, &regs->pl011_rlcr);
 122         }
 123 #endif
 124         writel(lcr, &regs->pl011_lcrh);
 125         return 0;
 126 }
 127
 128 static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
 129                                 int clock, int baudrate)
 130 {
 131         switch (type) {
 132         case TYPE_PL010: {
 133                 unsigned int divisor;
 134
 135                 switch (baudrate) {
 136                 case 9600:
 137                         divisor = UART_PL010_BAUD_9600;
 138                         break;
 139                 case 19200:
 140                         divisor = UART_PL010_BAUD_9600;
 141                         break;
 142                 case 38400:
 143                         divisor = UART_PL010_BAUD_38400;
 144                         break;
 145                 case 57600:
 146                         divisor = UART_PL010_BAUD_57600;
 147                         break;
 148                 case 115200:
 149                         divisor = UART_PL010_BAUD_115200;
 150                         break;
 151                 default:
 152                         divisor = UART_PL010_BAUD_38400;
 153                 }
 154
 155                 writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
 156                 writel(divisor & 0xff, &regs->pl010_lcrl);
 157
 158                 /* Finally, enable the UART */
 159                 writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
 160                 break;
 161         }
 162         case TYPE_PL011: {
 163                 unsigned int temp;
 164                 unsigned int divider;
 165                 unsigned int remainder;
 166                 unsigned int fraction;
 167
 168                 /*
 169                 * Set baud rate
 170                 *
 171                 * IBRD = UART_CLK / (16 * BAUD_RATE)
 172                 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
 173                 *               / (16 * BAUD_RATE))
 174                 */
 175                 temp = 16 * baudrate;
 176                 divider = clock / temp;
 177                 remainder = clock % temp;
 178                 temp = (8 * remainder) / baudrate;
 179                 fraction = (temp >> 1) + (temp & 1);
 180
 181                 writel(divider, &regs->pl011_ibrd);
 182                 writel(fraction, &regs->pl011_fbrd);
 183
 184                 set_line_control(regs);
 185                 /* Finally, enable the UART */
 186                 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
 187                        UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
 188                 break;
 189         }
 190         default:
 191                 return -EINVAL;
 192         }
 193
 194         return 0;
 195 }
 196
 197 #ifndef CONFIG_DM_SERIAL
 198 static void pl01x_serial_init_baud(int baudrate)
 199 {
 200         int clock = 0;
 201
 202 #if defined(CONFIG_PL010_SERIAL)
 203         pl01x_type = TYPE_PL010;
 204 #elif defined(CONFIG_PL011_SERIAL)
 205         pl01x_type = TYPE_PL011;
 206         clock = CONFIG_PL011_CLOCK;
 207 #endif
 208         base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
 209
 210         pl01x_generic_serial_init(base_regs, pl01x_type);
 211         pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
 212 }
 213
 214 /*
 215  * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
 216  * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
 217  * Versatile PB has four UARTs.
 218  */
 219 int pl01x_serial_init(void)
 220 {
 221         pl01x_serial_init_baud(CONFIG_BAUDRATE);
 222
 223         return 0;
 224 }
 225
 226 static void pl01x_serial_putc(const char c)
 227 {
 228         if (c == '\n')
 229                 while (pl01x_putc(base_regs, '\r') == -EAGAIN);
 230
 231         while (pl01x_putc(base_regs, c) == -EAGAIN);
 232 }
 233
 234 static int pl01x_serial_getc(void)
 235 {
 236         while (1) {
 237                 int ch = pl01x_getc(base_regs);
 238
 239                 if (ch == -EAGAIN) {
 240                         WATCHDOG_RESET();
 241                         continue;
 242                 }
 243
 244                 return ch;
 245         }
 246 }
 247
 248 static int pl01x_serial_tstc(void)
 249 {
 250         return pl01x_tstc(base_regs);
 251 }
 252
 253 static void pl01x_serial_setbrg(void)
 254 {
 255         /*
 256          * Flush FIFO and wait for non-busy before changing baudrate to avoid
 257          * crap in console
 258          */
 259         while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
 260                 WATCHDOG_RESET();
 261         while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
 262                 WATCHDOG_RESET();
 263         pl01x_serial_init_baud(gd->baudrate);
 264 }
 265
 266 static struct serial_device pl01x_serial_drv = {
 267         .name   = "pl01x_serial",
 268         .start  = pl01x_serial_init,
 269         .stop   = NULL,
 270         .setbrg = pl01x_serial_setbrg,
 271         .putc   = pl01x_serial_putc,
 272         .puts   = default_serial_puts,
 273         .getc   = pl01x_serial_getc,
 274         .tstc   = pl01x_serial_tstc,
 275 };
 276
 277 void pl01x_serial_initialize(void)
 278 {
 279         serial_register(&pl01x_serial_drv);
 280 }
 281
 282 __weak struct serial_device *default_serial_console(void)
 283 {
 284         return &pl01x_serial_drv;
 285 }
 286
 287 #endif /* nCONFIG_DM_SERIAL */
 288
 289 #ifdef CONFIG_DM_SERIAL
 290
 291 struct pl01x_priv {
 292         struct pl01x_regs *regs;
 293         enum pl01x_type type;
 294 };
 295
 296 static int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
 297 {
 298         struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
 299         struct pl01x_priv *priv = dev_get_priv(dev);
 300
 301         pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, baudrate);
 302
 303         return 0;
 304 }
 305
 306 static int pl01x_serial_probe(struct udevice *dev)
 307 {
 308         struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
 309         struct pl01x_priv *priv = dev_get_priv(dev);
 310
 311         priv->regs = (struct pl01x_regs *)plat->base;
 312         priv->type = plat->type;
 313         return pl01x_generic_serial_init(priv->regs, priv->type);
 314 }
 315
 316 static int pl01x_serial_getc(struct udevice *dev)
 317 {
 318         struct pl01x_priv *priv = dev_get_priv(dev);
 319
 320         return pl01x_getc(priv->regs);
 321 }
 322
 323 static int pl01x_serial_putc(struct udevice *dev, const char ch)
 324 {
 325         struct pl01x_priv *priv = dev_get_priv(dev);
 326
 327         return pl01x_putc(priv->regs, ch);
 328 }
 329
 330 static int pl01x_serial_pending(struct udevice *dev, bool input)
 331 {
 332         struct pl01x_priv *priv = dev_get_priv(dev);
 333         unsigned int fr = readl(&priv->regs->fr);
 334
 335         if (input)
 336                 return pl01x_tstc(priv->regs);
 337         else
 338                 return fr & UART_PL01x_FR_TXFF ? 0 : 1;
 339 }
 340
 341 static const struct dm_serial_ops pl01x_serial_ops = {
 342         .putc = pl01x_serial_putc,
 343         .pending = pl01x_serial_pending,
 344         .getc = pl01x_serial_getc,
 345         .setbrg = pl01x_serial_setbrg,
 346 };
 347
 348 U_BOOT_DRIVER(serial_pl01x) = {
 349         .name   = "serial_pl01x",
 350         .id     = UCLASS_SERIAL,
 351         .probe = pl01x_serial_probe,
 352         .ops    = &pl01x_serial_ops,
 353         .flags = DM_FLAG_PRE_RELOC,
 354 };
 355
 356 #endif