2 * SuperH SCIF device driver.
3 * Copyright (c) 2007,2008 Nobuhiro Iwamatsu
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <asm/processor.h>
23 #ifdef CFG_SCIF_CONSOLE
25 #if defined (CONFIG_CONS_SCIF0)
26 #define SCIF_BASE SCIF0_BASE
27 #elif defined (CONFIG_CONS_SCIF1)
28 #define SCIF_BASE SCIF1_BASE
29 #elif defined (CONFIG_CONS_SCIF2)
30 #define SCIF_BASE SCIF2_BASE
32 #error "Default SCIF doesn't set....."
36 #define SCSMR (vu_short *)(SCIF_BASE + 0x0)
37 #define SCBRR (vu_char *)(SCIF_BASE + 0x4)
38 #define SCSCR (vu_short *)(SCIF_BASE + 0x8)
39 #define SCFCR (vu_short *)(SCIF_BASE + 0x18)
40 #define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
41 #ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
42 # define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
43 # define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
44 # define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
46 # define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
47 # define SCFSR (vu_short *)(SCIF_BASE + 0x10)
48 # define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
51 #if defined(CONFIG_CPU_SH7780) || \
52 defined(CONFIG_CPU_SH7785)
53 # define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
54 # define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
55 # define SCLSR (vu_short *)(SCIF_BASE + 0x28)
56 # define SCRER (vu_short *)(SCIF_BASE + 0x2C)
58 # define FIFOLEVEL_MASK 0xFF
59 #elif defined(CONFIG_CPU_SH7763)
60 # if defined (CONFIG_CONS_SCIF2)
61 # define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
62 # define SCLSR (vu_short *)(SCIF_BASE + 0x24)
64 # define FIFOLEVEL_MASK 0x1F
66 # define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
67 # define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
68 # define SCLSR (vu_short *)(SCIF_BASE + 0x28)
69 # define SCRER (vu_short *)(SCIF_BASE + 0x2C)
71 # define FIFOLEVEL_MASK 0xFF
73 #elif defined(CONFIG_CPU_SH7750) || \
74 defined(CONFIG_CPU_SH7751) || \
75 defined(CONFIG_CPU_SH7722)
76 # define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
77 # define SCLSR (vu_short *)(SCIF_BASE + 0x24)
79 # define FIFOLEVEL_MASK 0x1F
80 #elif defined(CONFIG_CPU_SH7720)
81 # define SCLSR (vu_short *)(SCIF_BASE + 0x24)
82 # define LSR_ORER 0x0200
83 # define FIFOLEVEL_MASK 0x1F
84 #elif defined(CONFIG_CPU_SH7710) || \
85 defined(CONFIG_CPU_SH7712)
86 # define SCLSR SCFSR /* SCSSR */
88 # define FIFOLEVEL_MASK 0x1F
91 /* SCBRR register value setting */
92 #if defined(CONFIG_CPU_SH7720)
93 # define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
94 #else /* Generic SuperH */
95 # define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
98 #define SCR_RE (1 << 4)
99 #define SCR_TE (1 << 5)
100 #define FCR_RFRST (1 << 1) /* RFCL */
101 #define FCR_TFRST (1 << 2) /* TFCL */
102 #define FSR_DR (1 << 0)
103 #define FSR_RDF (1 << 1)
104 #define FSR_FER (1 << 3)
105 #define FSR_BRK (1 << 4)
106 #define FSR_FER (1 << 3)
107 #define FSR_TEND (1 << 6)
108 #define FSR_ER (1 << 7)
110 /*----------------------------------------------------------------------*/
112 void serial_setbrg(void)
114 DECLARE_GLOBAL_DATA_PTR;
115 *SCBRR = SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ);
118 int serial_init(void)
120 *SCSCR = (SCR_RE | SCR_TE);
123 *SCFCR = (FCR_RFRST | FCR_TFRST);
131 static int serial_rx_fifo_level(void)
134 return (*SCRFDR >> 0) & FIFOLEVEL_MASK;
136 return (*SCFDR >> 0) & FIFOLEVEL_MASK;
140 void serial_raw_putc(const char c)
142 unsigned int fsr_bits_to_clear;
145 if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */
146 fsr_bits_to_clear = FSR_TEND;
152 if (fsr_bits_to_clear != 0)
153 *SCFSR &= ~fsr_bits_to_clear;
156 void serial_putc(const char c)
159 serial_raw_putc('\r');
163 void serial_puts(const char *s)
166 while ((c = *s++) != 0)
170 int serial_tstc(void)
172 return serial_rx_fifo_level()? 1 : 0;
175 #define FSR_ERR_CLEAR 0x0063
176 #define RDRF_CLEAR 0x00fc
177 void handle_error(void)
181 *SCFSR = FSR_ERR_CLEAR;
186 int serial_getc_check(void)
188 unsigned short status;
192 if (status & (FSR_FER | FSR_ER | FSR_BRK))
194 if (*SCLSR & LSR_ORER)
196 return (status & (FSR_DR | FSR_RDF));
199 int serial_getc(void)
201 unsigned short status;
203 while (!serial_getc_check()) ;
210 if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
213 if (*SCLSR & LSR_ORER)
219 #endif /* CFG_SCIF_CONSOLE */