2 * SuperH SCIF device driver.
3 * Copyright (c) 2007,2008 Nobuhiro Iwamatsu
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <asm/processor.h>
23 #ifdef CFG_SCIF_CONSOLE
25 #if defined (CONFIG_CONS_SCIF0)
26 #define SCIF_BASE SCIF0_BASE
27 #elif defined (CONFIG_CONS_SCIF1)
28 #define SCIF_BASE SCIF1_BASE
30 #error "Default SCIF doesn't set....."
34 #define SCSMR (vu_short *)(SCIF_BASE + 0x0)
35 #define SCBRR (vu_char *)(SCIF_BASE + 0x4)
36 #define SCSCR (vu_short *)(SCIF_BASE + 0x8)
37 #define SCFCR (vu_short *)(SCIF_BASE + 0x18)
38 #define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
39 #ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
40 #define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
41 #define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
42 #define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
44 #define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
45 #define SCFSR (vu_short *)(SCIF_BASE + 0x10)
46 #define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
49 #if defined(CONFIG_CPU_SH7780) || \
50 defined(CONFIG_CPU_SH7785)
51 #define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
52 #define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
53 #define SCLSR (vu_short *)(SCIF_BASE + 0x28)
54 #define SCRER (vu_short *)(SCIF_BASE + 0x2C)
56 #elif defined(CONFIG_CPU_SH7750) || \
57 defined(CONFIG_CPU_SH7722)
58 #define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
59 #define SCLSR (vu_short *)(SCIF_BASE + 0x24)
61 #elif defined(CONFIG_CPU_SH7720)
62 #define SCLSR (vu_short *)(SCIF_BASE + 0x24)
63 #define LSR_ORER 0x0200
64 #elif defined(CONFIG_CPU_SH7710)
65 defined(CONFIG_CPU_SH7712)
66 #define SCLSR SCFSR /* SCSSR */
70 /* SCBRR register value setting */
71 #if defined(CONFIG_CPU_SH7720)
72 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
73 #else /* Generic SuperH */
74 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
77 #define SCR_RE (1 << 4)
78 #define SCR_TE (1 << 5)
79 #define FCR_RFRST (1 << 1) /* RFCL */
80 #define FCR_TFRST (1 << 2) /* TFCL */
81 #define FSR_DR (1 << 0)
82 #define FSR_RDF (1 << 1)
83 #define FSR_FER (1 << 3)
84 #define FSR_BRK (1 << 4)
85 #define FSR_FER (1 << 3)
86 #define FSR_TEND (1 << 6)
87 #define FSR_ER (1 << 7)
89 /*----------------------------------------------------------------------*/
91 void serial_setbrg (void)
93 DECLARE_GLOBAL_DATA_PTR;
94 *SCBRR = SCBRR_VALUE(gd->baudrate,CONFIG_SYS_CLK_FREQ);
97 int serial_init (void)
99 *SCSCR = (SCR_RE | SCR_TE);
102 *SCFCR = (FCR_RFRST | FCR_TFRST);
110 static int serial_tx_fifo_level (void)
112 return (*SCFDR >> 8) & 0x1F;
115 static int serial_rx_fifo_level (void)
117 return (*SCFDR >> 0) & 0x1F;
120 void serial_raw_putc (const char c)
122 unsigned int fsr_bits_to_clear;
125 if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */
126 fsr_bits_to_clear = FSR_TEND;
132 if (fsr_bits_to_clear != 0)
133 *SCFSR &= ~fsr_bits_to_clear;
136 void serial_putc (const char c)
139 serial_raw_putc ('\r');
143 void serial_puts (const char *s)
146 while ((c = *s++) != 0)
150 int serial_tstc (void)
152 return serial_rx_fifo_level() ? 1 : 0;
155 #define FSR_ERR_CLEAR 0x0063
156 #define RDRF_CLEAR 0x00fc
157 void handle_error( void ){
160 *SCFSR = FSR_ERR_CLEAR ;
165 int serial_getc_check( void ){
166 unsigned short status;
170 if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
172 if( *SCLSR & LSR_ORER )
174 return (status & ( FSR_DR | FSR_RDF ));
177 int serial_getc (void)
179 unsigned short status ;
181 while(!serial_getc_check());
186 *SCFSR = RDRF_CLEAR ;
188 if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
191 if( *SCLSR & LSR_ORER )
197 #endif /* CFG_SCIF_CONSOLE */