git.sur5r.net Git - u-boot/blob - drivers/serial/serial_stm32.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
   4  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <serial.h>
  11 #include <watchdog.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/stm32.h>
  14 #include "serial_stm32.h"
  15
  16 static void _stm32_serial_setbrg(fdt_addr_t base,
  17                                  struct stm32_uart_info *uart_info,
  18                                  u32 clock_rate,
  19                                  int baudrate)
  20 {
  21         bool stm32f4 = uart_info->stm32f4;
  22         u32 int_div, mantissa, fraction, oversampling;
  23
  24         int_div = DIV_ROUND_CLOSEST(clock_rate, baudrate);
  25
  26         if (int_div < 16) {
  27                 oversampling = 8;
  28                 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
  29         } else {
  30                 oversampling = 16;
  31                 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
  32         }
  33
  34         mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
  35         fraction = int_div % oversampling;
  36
  37         writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
  38 }
  39
  40 static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
  41 {
  42         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  43
  44         _stm32_serial_setbrg(plat->base, plat->uart_info,
  45                              plat->clock_rate, baudrate);
  46
  47         return 0;
  48 }
  49
  50 static int stm32_serial_getc(struct udevice *dev)
  51 {
  52         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  53         bool stm32f4 = plat->uart_info->stm32f4;
  54         fdt_addr_t base = plat->base;
  55         u32 isr = readl(base + ISR_OFFSET(stm32f4));
  56
  57         if ((isr & USART_ISR_RXNE) == 0)
  58                 return -EAGAIN;
  59
  60         if (isr & (USART_ISR_ORE)) {
  61                 if (!stm32f4)
  62                         setbits_le32(base + ICR_OFFSET, USART_ICR_ORECF);
  63                 else
  64                         readl(base + RDR_OFFSET(stm32f4));
  65                 return -EIO;
  66         }
  67
  68         return readl(base + RDR_OFFSET(stm32f4));
  69 }
  70
  71 static int _stm32_serial_putc(fdt_addr_t base,
  72                               struct stm32_uart_info *uart_info,
  73                               const char c)
  74 {
  75         bool stm32f4 = uart_info->stm32f4;
  76
  77         if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_TXE) == 0)
  78                 return -EAGAIN;
  79
  80         writel(c, base + TDR_OFFSET(stm32f4));
  81
  82         return 0;
  83 }
  84
  85 static int stm32_serial_putc(struct udevice *dev, const char c)
  86 {
  87         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  88
  89         return _stm32_serial_putc(plat->base, plat->uart_info, c);
  90 }
  91
  92 static int stm32_serial_pending(struct udevice *dev, bool input)
  93 {
  94         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  95         bool stm32f4 = plat->uart_info->stm32f4;
  96         fdt_addr_t base = plat->base;
  97
  98         if (input)
  99                 return readl(base + ISR_OFFSET(stm32f4)) &
 100                         USART_ISR_RXNE ? 1 : 0;
 101         else
 102                 return readl(base + ISR_OFFSET(stm32f4)) &
 103                         USART_ISR_TXE ? 0 : 1;
 104 }
 105
 106 static void _stm32_serial_init(fdt_addr_t base,
 107                                struct stm32_uart_info *uart_info)
 108 {
 109         bool stm32f4 = uart_info->stm32f4;
 110         u8 uart_enable_bit = uart_info->uart_enable_bit;
 111
 112         /* Disable uart-> enable fifo -> enable uart */
 113         clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
 114                      BIT(uart_enable_bit));
 115         if (uart_info->has_fifo)
 116                 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
 117         setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
 118                      BIT(uart_enable_bit));
 119 }
 120
 121 static int stm32_serial_probe(struct udevice *dev)
 122 {
 123         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
 124         struct clk clk;
 125         int ret;
 126
 127         plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
 128
 129         ret = clk_get_by_index(dev, 0, &clk);
 130         if (ret < 0)
 131                 return ret;
 132
 133         ret = clk_enable(&clk);
 134         if (ret) {
 135                 dev_err(dev, "failed to enable clock\n");
 136                 return ret;
 137         }
 138
 139         plat->clock_rate = clk_get_rate(&clk);
 140         if (plat->clock_rate < 0) {
 141                 clk_disable(&clk);
 142                 return plat->clock_rate;
 143         };
 144
 145         _stm32_serial_init(plat->base, plat->uart_info);
 146
 147         return 0;
 148 }
 149
 150 static const struct udevice_id stm32_serial_id[] = {
 151         { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
 152         { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
 153         { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
 154         {}
 155 };
 156
 157 static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
 158 {
 159         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
 160
 161         plat->base = devfdt_get_addr(dev);
 162         if (plat->base == FDT_ADDR_T_NONE)
 163                 return -EINVAL;
 164
 165         return 0;
 166 }
 167
 168 static const struct dm_serial_ops stm32_serial_ops = {
 169         .putc = stm32_serial_putc,
 170         .pending = stm32_serial_pending,
 171         .getc = stm32_serial_getc,
 172         .setbrg = stm32_serial_setbrg,
 173 };
 174
 175 U_BOOT_DRIVER(serial_stm32) = {
 176         .name = "serial_stm32",
 177         .id = UCLASS_SERIAL,
 178         .of_match = of_match_ptr(stm32_serial_id),
 179         .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
 180         .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
 181         .ops = &stm32_serial_ops,
 182         .probe = stm32_serial_probe,
 183         .flags = DM_FLAG_PRE_RELOC,
 184 };
 185
 186 #ifdef CONFIG_DEBUG_UART_STM32
 187 #include <debug_uart.h>
 188 static inline struct stm32_uart_info *_debug_uart_info(void)
 189 {
 190         struct stm32_uart_info *uart_info;
 191
 192 #if defined(CONFIG_STM32F4)
 193         uart_info = &stm32f4_info;
 194 #elif defined(CONFIG_STM32F7)
 195         uart_info = &stm32f7_info;
 196 #else
 197         uart_info = &stm32h7_info;
 198 #endif
 199         return uart_info;
 200 }
 201
 202 static inline void _debug_uart_init(void)
 203 {
 204         fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
 205         struct stm32_uart_info *uart_info = _debug_uart_info();
 206
 207         _stm32_serial_init(base, uart_info);
 208         _stm32_serial_setbrg(base, uart_info,
 209                              CONFIG_DEBUG_UART_CLOCK,
 210                              CONFIG_BAUDRATE);
 211         printf("DEBUG done\n");
 212 }
 213
 214 static inline void _debug_uart_putc(int c)
 215 {
 216         fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
 217         struct stm32_uart_info *uart_info = _debug_uart_info();
 218
 219         while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
 220                 WATCHDOG_RESET();
 221 }
 222
 223 DEBUG_UART_FUNCS
 224 #endif