2 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/stm32.h>
14 #include "serial_stm32.h"
16 static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
18 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
19 bool stm32f4 = plat->uart_info->stm32f4;
20 fdt_addr_t base = plat->base;
21 u32 int_div, mantissa, fraction, oversampling;
23 int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
27 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
30 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
33 mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
34 fraction = int_div % oversampling;
36 writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
41 static int stm32_serial_getc(struct udevice *dev)
43 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
44 bool stm32f4 = plat->uart_info->stm32f4;
45 fdt_addr_t base = plat->base;
46 u32 isr = readl(base + ISR_OFFSET(stm32f4));
48 if ((isr & USART_SR_FLAG_RXNE) == 0)
51 if (isr & USART_SR_FLAG_ORE) {
53 setbits_le32(base + ICR_OFFSET, USART_ICR_OREF);
55 readl(base + RDR_OFFSET(stm32f4));
59 return readl(base + RDR_OFFSET(stm32f4));
62 static int stm32_serial_putc(struct udevice *dev, const char c)
64 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
65 bool stm32f4 = plat->uart_info->stm32f4;
66 fdt_addr_t base = plat->base;
68 if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)
71 writel(c, base + TDR_OFFSET(stm32f4));
76 static int stm32_serial_pending(struct udevice *dev, bool input)
78 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
79 bool stm32f4 = plat->uart_info->stm32f4;
80 fdt_addr_t base = plat->base;
83 return readl(base + ISR_OFFSET(stm32f4)) &
84 USART_SR_FLAG_RXNE ? 1 : 0;
86 return readl(base + ISR_OFFSET(stm32f4)) &
87 USART_SR_FLAG_TXE ? 0 : 1;
90 static int stm32_serial_probe(struct udevice *dev)
92 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
94 fdt_addr_t base = plat->base;
99 plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
100 stm32f4 = plat->uart_info->stm32f4;
101 uart_enable_bit = plat->uart_info->uart_enable_bit;
103 ret = clk_get_by_index(dev, 0, &clk);
107 ret = clk_enable(&clk);
109 dev_err(dev, "failed to enable clock\n");
113 plat->clock_rate = clk_get_rate(&clk);
114 if (plat->clock_rate < 0) {
116 return plat->clock_rate;
119 /* Disable uart-> enable fifo-> enable uart */
120 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
121 BIT(uart_enable_bit));
122 if (plat->uart_info->has_fifo)
123 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
124 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
125 BIT(uart_enable_bit));
130 static const struct udevice_id stm32_serial_id[] = {
131 { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
132 { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
133 { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
137 static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
139 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
141 plat->base = devfdt_get_addr(dev);
142 if (plat->base == FDT_ADDR_T_NONE)
148 static const struct dm_serial_ops stm32_serial_ops = {
149 .putc = stm32_serial_putc,
150 .pending = stm32_serial_pending,
151 .getc = stm32_serial_getc,
152 .setbrg = stm32_serial_setbrg,
155 U_BOOT_DRIVER(serial_stm32) = {
156 .name = "serial_stm32",
158 .of_match = of_match_ptr(stm32_serial_id),
159 .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
160 .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
161 .ops = &stm32_serial_ops,
162 .probe = stm32_serial_probe,
163 .flags = DM_FLAG_PRE_RELOC,