git.sur5r.net Git - u-boot/blob - drivers/serial/serial_stm32x7.c

   1 /*
   2  * (C) Copyright 2016
   3  * Vikas Manocha, <vikas.manocha@st.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <asm/io.h>
  12 #include <serial.h>
  13 #include <asm/arch/stm32.h>
  14 #include "serial_stm32x7.h"
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
  19 {
  20         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  21         bool stm32f4 = plat->uart_info->stm32f4;
  22         fdt_addr_t base = plat->base;
  23         u32 int_div, mantissa, fraction, oversampling;
  24
  25         int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
  26
  27         if (int_div < 16) {
  28                 oversampling = 8;
  29                 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
  30         } else {
  31                 oversampling = 16;
  32                 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
  33         }
  34
  35         mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
  36         fraction = int_div % oversampling;
  37
  38         writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
  39
  40         return 0;
  41 }
  42
  43 static int stm32_serial_getc(struct udevice *dev)
  44 {
  45         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  46         bool stm32f4 = plat->uart_info->stm32f4;
  47         fdt_addr_t base = plat->base;
  48
  49         if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)
  50                 return -EAGAIN;
  51
  52         return readl(base + RDR_OFFSET(stm32f4));
  53 }
  54
  55 static int stm32_serial_putc(struct udevice *dev, const char c)
  56 {
  57         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  58         bool stm32f4 = plat->uart_info->stm32f4;
  59         fdt_addr_t base = plat->base;
  60
  61         if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)
  62                 return -EAGAIN;
  63
  64         writel(c, base + TDR_OFFSET(stm32f4));
  65
  66         return 0;
  67 }
  68
  69 static int stm32_serial_pending(struct udevice *dev, bool input)
  70 {
  71         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  72         bool stm32f4 = plat->uart_info->stm32f4;
  73         fdt_addr_t base = plat->base;
  74
  75         if (input)
  76                 return readl(base + ISR_OFFSET(stm32f4)) &
  77                         USART_SR_FLAG_RXNE ? 1 : 0;
  78         else
  79                 return readl(base + ISR_OFFSET(stm32f4)) &
  80                         USART_SR_FLAG_TXE ? 0 : 1;
  81 }
  82
  83 static int stm32_serial_probe(struct udevice *dev)
  84 {
  85         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  86         fdt_addr_t base = plat->base;
  87         bool stm32f4;
  88         u8 uart_enable_bit;
  89
  90         plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
  91         stm32f4 = plat->uart_info->stm32f4;
  92         uart_enable_bit = plat->uart_info->uart_enable_bit;
  93
  94 #ifdef CONFIG_CLK
  95         int ret;
  96         struct clk clk;
  97
  98         ret = clk_get_by_index(dev, 0, &clk);
  99         if (ret < 0)
 100                 return ret;
 101
 102         ret = clk_enable(&clk);
 103         if (ret) {
 104                 dev_err(dev, "failed to enable clock\n");
 105                 return ret;
 106         }
 107 #endif
 108
 109         plat->clock_rate = clk_get_rate(&clk);
 110         if (plat->clock_rate < 0) {
 111                 clk_disable(&clk);
 112                 return plat->clock_rate;
 113         };
 114
 115         /* Disable uart-> disable overrun-> enable uart */
 116         clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
 117                      BIT(uart_enable_bit));
 118         if (plat->uart_info->has_overrun_disable)
 119                 setbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);
 120         if (plat->uart_info->has_fifo)
 121                 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
 122         setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
 123                      BIT(uart_enable_bit));
 124
 125         return 0;
 126 }
 127
 128 #if CONFIG_IS_ENABLED(OF_CONTROL)
 129 static const struct udevice_id stm32_serial_id[] = {
 130         { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
 131         { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
 132         { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
 133         {}
 134 };
 135
 136 static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
 137 {
 138         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
 139
 140         plat->base = devfdt_get_addr(dev);
 141         if (plat->base == FDT_ADDR_T_NONE)
 142                 return -EINVAL;
 143
 144         return 0;
 145 }
 146 #endif
 147
 148 static const struct dm_serial_ops stm32_serial_ops = {
 149         .putc = stm32_serial_putc,
 150         .pending = stm32_serial_pending,
 151         .getc = stm32_serial_getc,
 152         .setbrg = stm32_serial_setbrg,
 153 };
 154
 155 U_BOOT_DRIVER(serial_stm32) = {
 156         .name = "serial_stm32x7",
 157         .id = UCLASS_SERIAL,
 158         .of_match = of_match_ptr(stm32_serial_id),
 159         .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
 160         .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
 161         .ops = &stm32_serial_ops,
 162         .probe = stm32_serial_probe,
 163         .flags = DM_FLAG_PRE_RELOC,
 164 };