2 * Copyright (C) 2012 Samsung Electronics
3 * R. Chandrasekar <rcsekar@samsung.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/arch/clk.h>
25 #include <asm/arch/pinmux.h>
26 #include <asm/arch/i2s-regs.h>
32 #define FIC_TX2COUNT(x) (((x) >> 24) & 0xf)
33 #define FIC_TX1COUNT(x) (((x) >> 16) & 0xf)
34 #define FIC_TXCOUNT(x) (((x) >> 8) & 0xf)
35 #define FIC_RXCOUNT(x) (((x) >> 0) & 0xf)
36 #define FICS_TXCOUNT(x) (((x) >> 8) & 0x7f)
38 #define TIMEOUT_I2S_TX 100 /* i2s transfer timeout */
41 * Sets the frame size for I2S LR clock
43 * @param i2s_reg i2s regiter address
44 * @param rfs Frame Size
46 static void i2s_set_lr_framesize(struct i2s_reg *i2s_reg, unsigned int rfs)
48 unsigned int mod = readl(&i2s_reg->mod);
50 mod &= ~MOD_RCLK_MASK;
54 mod |= MOD_RCLK_768FS;
57 mod |= MOD_RCLK_512FS;
60 mod |= MOD_RCLK_384FS;
63 mod |= MOD_RCLK_256FS;
67 writel(mod, &i2s_reg->mod);
71 * Sets the i2s transfer control
73 * @param i2s_reg i2s regiter address
74 * @param on 1 enable tx , 0 disable tx transfer
76 static void i2s_txctrl(struct i2s_reg *i2s_reg, int on)
78 unsigned int con = readl(&i2s_reg->con);
79 unsigned int mod = readl(&i2s_reg->mod) & ~MOD_MASK;
83 con &= ~CON_TXCH_PAUSE;
87 con |= CON_TXCH_PAUSE;
91 writel(mod, &i2s_reg->mod);
92 writel(con, &i2s_reg->con);
96 * set the bit clock frame size (in multiples of LRCLK)
98 * @param i2s_reg i2s regiter address
99 * @param bfs bit Frame Size
101 static void i2s_set_bitclk_framesize(struct i2s_reg *i2s_reg, unsigned bfs)
103 unsigned int mod = readl(&i2s_reg->mod);
105 mod &= ~MOD_BCLK_MASK;
109 mod |= MOD_BCLK_48FS;
112 mod |= MOD_BCLK_32FS;
115 mod |= MOD_BCLK_24FS;
118 mod |= MOD_BCLK_16FS;
123 writel(mod, &i2s_reg->mod);
127 * flushes the i2stx fifo
129 * @param i2s_reg i2s regiter address
130 * @param flush Tx fifo flush command (0x00 - do not flush
131 * 0x80 - flush tx fifo)
133 void i2s_fifo(struct i2s_reg *i2s_reg, unsigned int flush)
136 setbits_le32(&i2s_reg->fic, flush);
137 clrbits_le32(&i2s_reg->fic, flush);
141 * Set System Clock direction
143 * @param i2s_reg i2s regiter address
144 * @param dir Clock direction
146 * @return int value 0 for success, -1 in case of error
148 int i2s_set_sysclk_dir(struct i2s_reg *i2s_reg, int dir)
150 unsigned int mod = readl(&i2s_reg->mod);
152 if (dir == SND_SOC_CLOCK_IN)
155 mod &= ~MOD_CDCLKCON;
157 writel(mod, &i2s_reg->mod);
163 * Sets I2S Clcok format
165 * @param fmt i2s clock properties
166 * @param i2s_reg i2s regiter address
168 * @return int value 0 for success, -1 in case of error
170 int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt)
172 unsigned int mod = readl(&i2s_reg->mod);
173 unsigned int tmp = 0;
174 unsigned int ret = 0;
176 /* Format is priority */
177 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
178 case SND_SOC_DAIFMT_RIGHT_J:
182 case SND_SOC_DAIFMT_LEFT_J:
186 case SND_SOC_DAIFMT_I2S:
190 debug("%s: Invalid format priority [0x%x]\n", __func__,
191 (fmt & SND_SOC_DAIFMT_FORMAT_MASK));
196 * INV flag is relative to the FORMAT flag - if set it simply
197 * flips the polarity specified by the Standard
199 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
200 case SND_SOC_DAIFMT_NB_NF:
202 case SND_SOC_DAIFMT_NB_IF:
203 if (tmp & MOD_LR_RLOW)
209 debug("%s: Invalid clock ploarity input [0x%x]\n", __func__,
210 (fmt & SND_SOC_DAIFMT_INV_MASK));
214 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
215 case SND_SOC_DAIFMT_CBS_CFS:
218 case SND_SOC_DAIFMT_CBM_CFM:
219 /* Set default source clock in Master mode */
220 ret = i2s_set_sysclk_dir(i2s_reg, SND_SOC_CLOCK_OUT);
222 debug("%s:set i2s clock direction failed\n", __func__);
227 debug("%s: Invalid master selection [0x%x]\n", __func__,
228 (fmt & SND_SOC_DAIFMT_MASTER_MASK));
232 mod &= ~(MOD_SDF_MASK | MOD_LR_RLOW | MOD_SLAVE);
234 writel(mod, &i2s_reg->mod);
240 * Sets the sample width in bits
242 * @param blc samplewidth (size of sample in bits)
243 * @param i2s_reg i2s regiter address
245 * @return int value 0 for success, -1 in case of error
247 int i2s_set_samplesize(struct i2s_reg *i2s_reg, unsigned int blc)
249 unsigned int mod = readl(&i2s_reg->mod);
251 mod &= ~MOD_BLCP_MASK;
252 mod &= ~MOD_BLC_MASK;
256 mod |= MOD_BLCP_8BIT;
260 mod |= MOD_BLCP_16BIT;
261 mod |= MOD_BLC_16BIT;
264 mod |= MOD_BLCP_24BIT;
265 mod |= MOD_BLC_24BIT;
268 debug("%s: Invalid sample size input [0x%x]\n",
272 writel(mod, &i2s_reg->mod);
277 int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned int *data,
278 unsigned long data_size)
282 struct i2s_reg *i2s_reg =
283 (struct i2s_reg *)pi2s_tx->base_address;
285 if (data_size < FIFO_LENGTH) {
286 debug("%s : Invalid data size\n", __func__);
287 return -1; /* invalid pcm data size */
290 /* fill the tx buffer before stating the tx transmit */
291 for (i = 0; i < FIFO_LENGTH; i++)
292 writel(*data++, &i2s_reg->txd);
294 data_size -= FIFO_LENGTH;
295 i2s_txctrl(i2s_reg, I2S_TX_ON);
297 while (data_size > 0) {
298 start = get_timer(0);
299 if (!(CON_TXFIFO_FULL & (readl(&i2s_reg->con)))) {
300 writel(*data++, &i2s_reg->txd);
303 if (get_timer(start) > TIMEOUT_I2S_TX) {
304 i2s_txctrl(i2s_reg, I2S_TX_OFF);
305 debug("%s: I2S Transfer Timeout\n", __func__);
310 i2s_txctrl(i2s_reg, I2S_TX_OFF);
315 int i2s_tx_init(struct i2stx_info *pi2s_tx)
318 struct i2s_reg *i2s_reg =
319 (struct i2s_reg *)pi2s_tx->base_address;
321 /* Initialize GPIO for I2s */
322 exynos_pinmux_config(PERIPH_ID_I2S1, 0);
325 ret = set_epll_clk(pi2s_tx->audio_pll_clk);
327 debug("%s: epll clock set rate falied\n", __func__);
331 /* Select Clk Source for Audio1 */
332 set_i2s_clk_source();
334 /* Set Prescaler to get MCLK */
335 set_i2s_clk_prescaler(pi2s_tx->audio_pll_clk,
336 (pi2s_tx->samplingrate * (pi2s_tx->rfs)));
338 /* Configure I2s format */
339 ret = i2s_set_fmt(i2s_reg, (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
340 SND_SOC_DAIFMT_CBM_CFM));
342 i2s_set_lr_framesize(i2s_reg, pi2s_tx->rfs);
343 ret = i2s_set_samplesize(i2s_reg, pi2s_tx->bitspersample);
345 debug("%s:set sample rate failed\n", __func__);
349 i2s_set_bitclk_framesize(i2s_reg, pi2s_tx->bfs);
350 /* disable i2s transfer flag and flush the fifo */
351 i2s_txctrl(i2s_reg, I2S_TX_OFF);
352 i2s_fifo(i2s_reg, FIC_TXFLUSH);
354 debug("%s: failed\n", __func__);