4 bool "Enable Driver Model for SPI drivers"
7 Enable driver model for SPI. The SPI slave interface
8 (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
9 the SPI uclass. Drivers provide methods to access the SPI
10 buses that they control. The uclass interface is defined in
11 include/spi.h. The existing spi_slave structure is attached
12 as 'parent data' to every slave on each bus. Slaves
13 typically use driver-private data instead of extending the
17 bool "Sandbox SPI driver"
18 depends on SANDBOX && DM
20 Enable SPI support for sandbox. This is an emulation of a real SPI
21 bus. Devices can be attached to the bus using the device tree
22 which specifies the driver to use. As an example, see this device
23 tree fragment from sandbox.dts. It shows that the SPI bus has a
24 single flash device on chip select 0 which is emulated by the driver
25 for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c.
31 compatible = "sandbox,spi";
32 cs-gpios = <0>, <&gpio_a 0>;
35 compatible = "spansion,m25p16", "sandbox,spi-flash";
36 spi-max-frequency = <40000000>;
37 sandbox,filename = "spi.bin";
42 bool "Designware SPI driver"
45 Enable the Designware SPI driver. This driver can be used to
46 access the SPI NOR flash on platforms embedding this Designware
50 bool "Cadence QSPI driver"
53 Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
54 used to access the SPI NOR flash on platforms embedding this
58 bool "Xilinx SPI driver"
61 Enable the Xilinx SPI driver from the Xilinx EDK. This SPI
62 controller support 8 bit SPI transfers only, with or w/o FIFO.
63 For more info on Xilinx SPI Register Definitions and Overview
64 see driver file - drivers/spi/xilinx_spi.c
67 bool "Zynq SPI driver"
68 depends on DM_SPI && (ARCH_ZYNQ || TARGET_XILINX_ZYNQMP)
70 Enable the Zynq SPI driver. This driver can be used to
71 access the SPI NOR flash on platforms embedding this Zynq
74 endmenu # menu "SPI Support"