4 bool "Enable Driver Model for SPI drivers"
7 Enable driver model for SPI. The SPI slave interface
8 (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
9 the SPI uclass. Drivers provide methods to access the SPI
10 buses that they control. The uclass interface is defined in
11 include/spi.h. The existing spi_slave structure is attached
12 as 'parent data' to every slave on each bus. Slaves
13 typically use driver-private data instead of extending the
19 bool "Cadence QSPI driver"
21 Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
22 used to access the SPI NOR flash on platforms embedding this
26 bool "Designware SPI driver"
28 Enable the Designware SPI driver. This driver can be used to
29 access the SPI NOR flash on platforms embedding this Designware
33 bool "Samsung Exynos SPI driver"
35 Enable the Samsung Exynos SPI driver. This driver can be used to
36 access the SPI NOR flash on platforms embedding this Samsung
40 bool "Freescale DSPI driver"
42 Enable the Freescale DSPI driver. This driver can be used to
43 access the SPI NOR flash and SPI Data flash on platforms embedding
44 this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
48 bool "Freescale QSPI driver"
50 Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
51 used to access the SPI NOR flash on platforms embedding this
55 bool "Sandbox SPI driver"
56 depends on SANDBOX && DM
58 Enable SPI support for sandbox. This is an emulation of a real SPI
59 bus. Devices can be attached to the bus using the device tree
60 which specifies the driver to use. As an example, see this device
61 tree fragment from sandbox.dts. It shows that the SPI bus has a
62 single flash device on chip select 0 which is emulated by the driver
63 for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c.
69 compatible = "sandbox,spi";
70 cs-gpios = <0>, <&gpio_a 0>;
73 compatible = "spansion,m25p16", "sandbox,spi-flash";
74 spi-max-frequency = <40000000>;
75 sandbox,filename = "spi.bin";
80 bool "Xilinx SPI driver"
82 Enable the Xilinx SPI driver from the Xilinx EDK. This SPI
83 controller support 8 bit SPI transfers only, with or w/o FIFO.
84 For more info on Xilinx SPI Register Definitions and Overview
85 see driver file - drivers/spi/xilinx_spi.c
88 bool "Zynq SPI driver"
89 depends on ARCH_ZYNQ || TARGET_XILINX_ZYNQMP
91 Enable the Zynq SPI driver. This driver can be used to
92 access the SPI NOR flash on platforms embedding this Zynq
98 bool "Freescale eSPI driver"
100 Enable the Freescale eSPI driver. This driver can be used to
101 access the SPI interface and SPI NOR flash on platforms embedding
102 this Freescale eSPI IP core.
105 bool "TI QSPI driver"
107 Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
108 This driver support spi flash single, quad and memory reads.
110 endmenu # menu "SPI Support"