2 * Copyright (C) 2007 Atmel Corporation
4 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/clk.h>
17 #include <asm/arch/hardware.h>
19 #include <asm/arch/at91_spi.h>
25 #include "atmel_spi.h"
27 DECLARE_GLOBAL_DATA_PTR;
31 static int spi_has_wdrbt(struct atmel_spi_slave *slave)
35 ver = spi_readl(slave, VERSION);
37 return (ATMEL_SPI_VERSION_REV(ver) >= 0x210);
45 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
46 unsigned int max_hz, unsigned int mode)
48 struct atmel_spi_slave *as;
53 if (!spi_cs_is_valid(bus, cs))
58 regs = (void *)ATMEL_BASE_SPI0;
60 #ifdef ATMEL_BASE_SPI1
62 regs = (void *)ATMEL_BASE_SPI1;
65 #ifdef ATMEL_BASE_SPI2
67 regs = (void *)ATMEL_BASE_SPI2;
70 #ifdef ATMEL_BASE_SPI3
72 regs = (void *)ATMEL_BASE_SPI3;
80 scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz;
81 if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
82 /* Too low max SCK rate */
87 csrx = ATMEL_SPI_CSRx_SCBR(scbr);
88 csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
89 if (!(mode & SPI_CPHA))
90 csrx |= ATMEL_SPI_CSRx_NCPHA;
92 csrx |= ATMEL_SPI_CSRx_CPOL;
94 as = spi_alloc_slave(struct atmel_spi_slave, bus, cs);
99 as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS
100 | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf);
101 if (spi_has_wdrbt(as))
102 as->mr |= ATMEL_SPI_MR_WDRBT;
104 spi_writel(as, CSR(cs), csrx);
109 void spi_free_slave(struct spi_slave *slave)
111 struct atmel_spi_slave *as = to_atmel_spi(slave);
116 int spi_claim_bus(struct spi_slave *slave)
118 struct atmel_spi_slave *as = to_atmel_spi(slave);
120 /* Enable the SPI hardware */
121 spi_writel(as, CR, ATMEL_SPI_CR_SPIEN);
124 * Select the slave. This should set SCK to the correct
125 * initial state, etc.
127 spi_writel(as, MR, as->mr);
132 void spi_release_bus(struct spi_slave *slave)
134 struct atmel_spi_slave *as = to_atmel_spi(slave);
136 /* Disable the SPI hardware */
137 spi_writel(as, CR, ATMEL_SPI_CR_SPIDIS);
140 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
141 const void *dout, void *din, unsigned long flags)
143 struct atmel_spi_slave *as = to_atmel_spi(slave);
148 const u8 *txp = dout;
153 /* Finish any previously submitted transfers */
157 * TODO: The controller can do non-multiple-of-8 bit
158 * transfers, but this driver currently doesn't support it.
160 * It's also not clear how such transfers are supposed to be
161 * represented as a stream of bytes...this is a limitation of
162 * the current SPI interface.
165 /* Errors always terminate an ongoing transfer */
166 flags |= SPI_XFER_END;
173 * The controller can do automatic CS control, but it is
174 * somewhat quirky, and it doesn't really buy us much anyway
175 * in the context of U-Boot.
177 if (flags & SPI_XFER_BEGIN) {
178 spi_cs_activate(slave);
180 * sometimes the RDR is not empty when we get here,
181 * in theory that should not happen, but it DOES happen.
182 * Read it here to be on the safe side.
183 * That also clears the OVRES flag. Required if the
184 * following loop exits due to OVRES!
189 for (len_tx = 0, len_rx = 0; len_rx < len; ) {
190 status = spi_readl(as, SR);
192 if (status & ATMEL_SPI_SR_OVRES)
195 if (len_tx < len && (status & ATMEL_SPI_SR_TDRE)) {
200 spi_writel(as, TDR, value);
203 if (status & ATMEL_SPI_SR_RDRF) {
204 value = spi_readl(as, RDR);
212 if (flags & SPI_XFER_END) {
214 * Wait until the transfer is completely done before
218 status = spi_readl(as, SR);
219 } while (!(status & ATMEL_SPI_SR_TXEMPTY));
221 spi_cs_deactivate(slave);
229 #define MAX_CS_COUNT 4
231 struct atmel_spi_platdata {
232 struct at91_spi *regs;
235 struct atmel_spi_priv {
236 unsigned int freq; /* Default frequency */
239 #ifdef CONFIG_DM_GPIO
240 struct gpio_desc cs_gpios[MAX_CS_COUNT];
244 static int atmel_spi_claim_bus(struct udevice *dev)
246 struct udevice *bus = dev_get_parent(dev);
247 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
248 struct atmel_spi_priv *priv = dev_get_priv(bus);
249 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
250 struct at91_spi *reg_base = bus_plat->regs;
251 u32 cs = slave_plat->cs;
252 u32 freq = priv->freq;
253 u32 scbr, csrx, mode;
255 scbr = (priv->bus_clk_rate + freq - 1) / freq;
256 if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
262 csrx = ATMEL_SPI_CSRx_SCBR(scbr);
263 csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
265 if (!(priv->mode & SPI_CPHA))
266 csrx |= ATMEL_SPI_CSRx_NCPHA;
267 if (priv->mode & SPI_CPOL)
268 csrx |= ATMEL_SPI_CSRx_CPOL;
270 writel(csrx, ®_base->csr[cs]);
272 mode = ATMEL_SPI_MR_MSTR |
273 ATMEL_SPI_MR_MODFDIS |
275 ATMEL_SPI_MR_PCS(~(1 << cs));
277 writel(mode, ®_base->mr);
279 writel(ATMEL_SPI_CR_SPIEN, ®_base->cr);
284 static int atmel_spi_release_bus(struct udevice *dev)
286 struct udevice *bus = dev_get_parent(dev);
287 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
289 writel(ATMEL_SPI_CR_SPIDIS, &bus_plat->regs->cr);
294 static void atmel_spi_cs_activate(struct udevice *dev)
296 #ifdef CONFIG_DM_GPIO
297 struct udevice *bus = dev_get_parent(dev);
298 struct atmel_spi_priv *priv = dev_get_priv(bus);
299 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
300 u32 cs = slave_plat->cs;
302 if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
305 dm_gpio_set_value(&priv->cs_gpios[cs], 0);
309 static void atmel_spi_cs_deactivate(struct udevice *dev)
311 #ifdef CONFIG_DM_GPIO
312 struct udevice *bus = dev_get_parent(dev);
313 struct atmel_spi_priv *priv = dev_get_priv(bus);
314 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
315 u32 cs = slave_plat->cs;
317 if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
320 dm_gpio_set_value(&priv->cs_gpios[cs], 1);
324 static int atmel_spi_xfer(struct udevice *dev, unsigned int bitlen,
325 const void *dout, void *din, unsigned long flags)
327 struct udevice *bus = dev_get_parent(dev);
328 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
329 struct at91_spi *reg_base = bus_plat->regs;
331 u32 len_tx, len_rx, len;
333 const u8 *txp = dout;
341 * The controller can do non-multiple-of-8 bit
342 * transfers, but this driver currently doesn't support it.
344 * It's also not clear how such transfers are supposed to be
345 * represented as a stream of bytes...this is a limitation of
346 * the current SPI interface.
349 /* Errors always terminate an ongoing transfer */
350 flags |= SPI_XFER_END;
357 * The controller can do automatic CS control, but it is
358 * somewhat quirky, and it doesn't really buy us much anyway
359 * in the context of U-Boot.
361 if (flags & SPI_XFER_BEGIN) {
362 atmel_spi_cs_activate(dev);
365 * sometimes the RDR is not empty when we get here,
366 * in theory that should not happen, but it DOES happen.
367 * Read it here to be on the safe side.
368 * That also clears the OVRES flag. Required if the
369 * following loop exits due to OVRES!
371 readl(®_base->rdr);
374 for (len_tx = 0, len_rx = 0; len_rx < len; ) {
375 status = readl(®_base->sr);
377 if (status & ATMEL_SPI_SR_OVRES)
380 if ((len_tx < len) && (status & ATMEL_SPI_SR_TDRE)) {
385 writel(value, ®_base->tdr);
389 if (status & ATMEL_SPI_SR_RDRF) {
390 value = readl(®_base->rdr);
398 if (flags & SPI_XFER_END) {
400 * Wait until the transfer is completely done before
403 wait_for_bit_le32(®_base->sr,
404 ATMEL_SPI_SR_TXEMPTY, true, 1000, false);
406 atmel_spi_cs_deactivate(dev);
412 static int atmel_spi_set_speed(struct udevice *bus, uint speed)
414 struct atmel_spi_priv *priv = dev_get_priv(bus);
421 static int atmel_spi_set_mode(struct udevice *bus, uint mode)
423 struct atmel_spi_priv *priv = dev_get_priv(bus);
430 static const struct dm_spi_ops atmel_spi_ops = {
431 .claim_bus = atmel_spi_claim_bus,
432 .release_bus = atmel_spi_release_bus,
433 .xfer = atmel_spi_xfer,
434 .set_speed = atmel_spi_set_speed,
435 .set_mode = atmel_spi_set_mode,
437 * cs_info is not needed, since we require all chip selects to be
438 * in the device tree explicitly
442 static int atmel_spi_enable_clk(struct udevice *bus)
444 struct atmel_spi_priv *priv = dev_get_priv(bus);
449 ret = clk_get_by_index(bus, 0, &clk);
453 ret = clk_enable(&clk);
457 clk_rate = clk_get_rate(&clk);
461 priv->bus_clk_rate = clk_rate;
468 static int atmel_spi_probe(struct udevice *bus)
470 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
473 ret = atmel_spi_enable_clk(bus);
477 bus_plat->regs = (struct at91_spi *)devfdt_get_addr(bus);
479 #ifdef CONFIG_DM_GPIO
480 struct atmel_spi_priv *priv = dev_get_priv(bus);
483 ret = gpio_request_list_by_name(bus, "cs-gpios", priv->cs_gpios,
484 ARRAY_SIZE(priv->cs_gpios), 0);
486 pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
490 for(i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
491 if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
494 dm_gpio_set_dir_flags(&priv->cs_gpios[i],
495 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
499 writel(ATMEL_SPI_CR_SWRST, &bus_plat->regs->cr);
504 static const struct udevice_id atmel_spi_ids[] = {
505 { .compatible = "atmel,at91rm9200-spi" },
509 U_BOOT_DRIVER(atmel_spi) = {
512 .of_match = atmel_spi_ids,
513 .ops = &atmel_spi_ops,
514 .platdata_auto_alloc_size = sizeof(struct atmel_spi_platdata),
515 .priv_auto_alloc_size = sizeof(struct atmel_spi_priv),
516 .probe = atmel_spi_probe,