1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
5 * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
6 * Copyright (C) 2000-2010 Broadcom Corporation
7 * Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
18 DECLARE_GLOBAL_DATA_PTR;
22 #define SPI_MAX_SYNC_CLOCK 30000000
24 /* SPI Control register */
25 #define SPI_CTL_REG 0x000
26 #define SPI_CTL_CS_POL_SHIFT 0
27 #define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT)
28 #define SPI_CTL_CLK_GATE_SHIFT 16
29 #define SPI_CTL_CLK_GATE_MASK (1 << SPI_CTL_CLK_GATE_SHIFT)
30 #define SPI_CTL_CLK_POL_SHIFT 17
31 #define SPI_CTL_CLK_POL_MASK (1 << SPI_CTL_CLK_POL_SHIFT)
33 /* SPI Interrupts registers */
34 #define SPI_IR_STAT_REG 0x008
35 #define SPI_IR_ST_MASK_REG 0x00c
36 #define SPI_IR_MASK_REG 0x010
38 #define SPI_IR_CLEAR_ALL 0xff001f1f
40 /* SPI Ping-Pong Command registers */
41 #define SPI_CMD_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x00)
42 #define SPI_CMD_OP_SHIFT 0
43 #define SPI_CMD_OP_START (0x1 << SPI_CMD_OP_SHIFT)
44 #define SPI_CMD_PFL_SHIFT 8
45 #define SPI_CMD_PFL_MASK (0x7 << SPI_CMD_PFL_SHIFT)
46 #define SPI_CMD_SLAVE_SHIFT 12
47 #define SPI_CMD_SLAVE_MASK (0x7 << SPI_CMD_SLAVE_SHIFT)
49 /* SPI Ping-Pong Status registers */
50 #define SPI_STAT_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x04)
51 #define SPI_STAT_SRCBUSY_SHIFT 1
52 #define SPI_STAT_SRCBUSY_MASK (1 << SPI_STAT_SRCBUSY_SHIFT)
54 /* SPI Profile Clock registers */
55 #define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00)
56 #define SPI_PFL_CLK_FREQ_SHIFT 0
57 #define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT)
58 #define SPI_PFL_CLK_RSTLOOP_SHIFT 15
59 #define SPI_PFL_CLK_RSTLOOP_MASK (1 << SPI_PFL_CLK_RSTLOOP_SHIFT)
61 /* SPI Profile Signal registers */
62 #define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04)
63 #define SPI_PFL_SIG_LATCHRIS_SHIFT 12
64 #define SPI_PFL_SIG_LATCHRIS_MASK (1 << SPI_PFL_SIG_LATCHRIS_SHIFT)
65 #define SPI_PFL_SIG_LAUNCHRIS_SHIFT 13
66 #define SPI_PFL_SIG_LAUNCHRIS_MASK (1 << SPI_PFL_SIG_LAUNCHRIS_SHIFT)
67 #define SPI_PFL_SIG_ASYNCIN_SHIFT 16
68 #define SPI_PFL_SIG_ASYNCIN_MASK (1 << SPI_PFL_SIG_ASYNCIN_SHIFT)
70 /* SPI Profile Mode registers */
71 #define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08)
72 #define SPI_PFL_MODE_FILL_SHIFT 0
73 #define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT)
74 #define SPI_PFL_MODE_MDRDSZ_SHIFT 16
75 #define SPI_PFL_MODE_MDRDSZ_MASK (1 << SPI_PFL_MODE_MDRDSZ_SHIFT)
76 #define SPI_PFL_MODE_MDWRSZ_SHIFT 18
77 #define SPI_PFL_MODE_MDWRSZ_MASK (1 << SPI_PFL_MODE_MDWRSZ_SHIFT)
78 #define SPI_PFL_MODE_3WIRE_SHIFT 20
79 #define SPI_PFL_MODE_3WIRE_MASK (1 << SPI_PFL_MODE_3WIRE_SHIFT)
81 /* SPI Ping-Pong FIFO registers */
82 #define HSSPI_FIFO_SIZE 0x200
83 #define HSSPI_FIFO_BASE (0x200 + \
84 (HSSPI_FIFO_SIZE * HSSPI_PP))
86 /* SPI Ping-Pong FIFO OP register */
87 #define HSSPI_FIFO_OP_SIZE 0x2
88 #define HSSPI_FIFO_OP_REG (HSSPI_FIFO_BASE + 0x00)
89 #define HSSPI_FIFO_OP_BYTES_SHIFT 0
90 #define HSSPI_FIFO_OP_BYTES_MASK (0x3ff << HSSPI_FIFO_OP_BYTES_SHIFT)
91 #define HSSPI_FIFO_OP_MBIT_SHIFT 11
92 #define HSSPI_FIFO_OP_MBIT_MASK (1 << HSSPI_FIFO_OP_MBIT_SHIFT)
93 #define HSSPI_FIFO_OP_CODE_SHIFT 13
94 #define HSSPI_FIFO_OP_READ_WRITE (1 << HSSPI_FIFO_OP_CODE_SHIFT)
95 #define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT)
96 #define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT)
98 struct bcm63xx_hsspi_priv {
106 static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,
107 struct spi_cs_info *info)
109 struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
111 if (cs >= priv->num_cs) {
112 printf("no cs %u\n", cs);
119 static int bcm63xx_hsspi_set_mode(struct udevice *bus, uint mode)
121 struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
125 setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
127 clrbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
132 static int bcm63xx_hsspi_set_speed(struct udevice *bus, uint speed)
134 struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
141 static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv,
142 struct dm_spi_slave_platdata *plat)
147 set = DIV_ROUND_UP(priv->clk_rate, priv->speed);
148 set = DIV_ROUND_UP(2048, set);
149 set &= SPI_PFL_CLK_FREQ_MASK;
150 set |= SPI_PFL_CLK_RSTLOOP_MASK;
151 writel_be(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));
155 clr = SPI_PFL_SIG_LAUNCHRIS_MASK |
156 SPI_PFL_SIG_LATCHRIS_MASK |
157 SPI_PFL_SIG_ASYNCIN_MASK;
159 /* latch/launch config */
160 if (plat->mode & SPI_CPHA)
161 set |= SPI_PFL_SIG_LAUNCHRIS_MASK;
163 set |= SPI_PFL_SIG_LATCHRIS_MASK;
166 if (priv->speed > SPI_MAX_SYNC_CLOCK)
167 set |= SPI_PFL_SIG_ASYNCIN_MASK;
169 clrsetbits_be32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);
175 /* invert cs polarity */
176 if (priv->cs_pols & BIT(plat->cs))
177 clr |= BIT(plat->cs);
179 set |= BIT(plat->cs);
181 /* invert dummy cs polarity */
182 if (priv->cs_pols & BIT(!plat->cs))
183 clr |= BIT(!plat->cs);
185 set |= BIT(!plat->cs);
187 clrsetbits_be32(priv->regs + SPI_CTL_REG, clr, set);
190 static void bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv *priv)
192 /* restore cs polarities */
193 clrsetbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK,
198 * BCM63xx HSSPI driver doesn't allow keeping CS active between transfers
199 * because they are controlled by HW.
200 * However, it provides a mechanism to prepend write transfers prior to read
201 * transfers (with a maximum prepend of 15 bytes), which is usually enough for
202 * SPI-connected flashes since reading requires prepending a write transfer of
203 * 5 bytes. On the other hand it also provides a way to invert each CS
204 * polarity, not only between transfers like the older BCM63xx SPI driver, but
205 * also the rest of the time.
207 * Instead of using the prepend mechanism, this implementation inverts the
208 * polarity of both the desired CS and another dummy CS when the bus is
209 * claimed. This way, the dummy CS is restored to its inactive value when
210 * transfers are issued and the desired CS is preserved in its active value
211 * all the time. This hack is also used in the upstream linux driver and
212 * allows keeping CS active between trasnfers even if the HW doesn't give
215 static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
216 const void *dout, void *din, unsigned long flags)
218 struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
219 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
220 size_t data_bytes = bitlen / 8;
221 size_t step_size = HSSPI_FIFO_SIZE;
224 const uint8_t *tx = dout;
227 if (flags & SPI_XFER_BEGIN)
228 bcm63xx_hsspi_activate_cs(priv, plat);
232 opcode = HSSPI_FIFO_OP_READ_WRITE;
234 opcode = HSSPI_FIFO_OP_CODE_R;
236 opcode = HSSPI_FIFO_OP_CODE_W;
238 if (opcode != HSSPI_FIFO_OP_CODE_R)
239 step_size -= HSSPI_FIFO_OP_SIZE;
242 if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) ||
243 (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL))
244 opcode |= HSSPI_FIFO_OP_MBIT_MASK;
247 val = SPI_PFL_MODE_FILL_MASK |
248 SPI_PFL_MODE_MDRDSZ_MASK |
249 SPI_PFL_MODE_MDWRSZ_MASK;
250 if (plat->mode & SPI_3WIRE)
251 val |= SPI_PFL_MODE_3WIRE_MASK;
252 writel_be(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
255 while (data_bytes > 0) {
256 size_t curr_step = min(step_size, data_bytes);
261 memcpy_toio(priv->regs + HSSPI_FIFO_BASE +
262 HSSPI_FIFO_OP_SIZE, tx, curr_step);
266 /* set fifo operation */
267 writew_be(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK),
268 priv->regs + HSSPI_FIFO_OP_REG);
270 /* issue the transfer */
271 val = SPI_CMD_OP_START;
272 val |= (plat->cs << SPI_CMD_PFL_SHIFT) &
274 val |= (!plat->cs << SPI_CMD_SLAVE_SHIFT) &
276 writel_be(val, priv->regs + SPI_CMD_REG);
278 /* wait for completion */
279 ret = wait_for_bit_be32(priv->regs + SPI_STAT_REG,
280 SPI_STAT_SRCBUSY_MASK, false,
283 printf("interrupt timeout\n");
289 memcpy_fromio(rx, priv->regs + HSSPI_FIFO_BASE,
294 data_bytes -= curr_step;
297 if (flags & SPI_XFER_END)
298 bcm63xx_hsspi_deactivate_cs(priv);
303 static const struct dm_spi_ops bcm63xx_hsspi_ops = {
304 .cs_info = bcm63xx_hsspi_cs_info,
305 .set_mode = bcm63xx_hsspi_set_mode,
306 .set_speed = bcm63xx_hsspi_set_speed,
307 .xfer = bcm63xx_hsspi_xfer,
310 static const struct udevice_id bcm63xx_hsspi_ids[] = {
311 { .compatible = "brcm,bcm6328-hsspi", },
315 static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev)
317 struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
318 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
321 if (plat->cs >= priv->num_cs) {
322 printf("no cs %u\n", plat->cs);
327 if (plat->mode & SPI_CS_HIGH)
328 priv->cs_pols |= BIT(plat->cs);
330 priv->cs_pols &= ~BIT(plat->cs);
335 static int bcm63xx_hsspi_probe(struct udevice *dev)
337 struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev);
338 struct reset_ctl rst_ctl;
344 addr = devfdt_get_addr_size_index(dev, 0, &size);
345 if (addr == FDT_ADDR_T_NONE)
348 priv->regs = ioremap(addr, size);
349 priv->num_cs = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
353 ret = clk_get_by_name(dev, "hsspi", &clk);
357 ret = clk_enable(&clk);
361 ret = clk_free(&clk);
366 ret = clk_get_by_name(dev, "pll", &clk);
370 priv->clk_rate = clk_get_rate(&clk);
372 ret = clk_free(&clk);
377 ret = reset_get_by_index(dev, 0, &rst_ctl);
381 ret = reset_deassert(&rst_ctl);
385 ret = reset_free(&rst_ctl);
389 /* initialize hardware */
390 writel_be(0, priv->regs + SPI_IR_MASK_REG);
392 /* clear pending interrupts */
393 writel_be(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG);
395 /* enable clk gate */
396 setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK);
398 /* read default cs polarities */
399 priv->cs_pols = readl_be(priv->regs + SPI_CTL_REG) &
405 U_BOOT_DRIVER(bcm63xx_hsspi) = {
406 .name = "bcm63xx_hsspi",
408 .of_match = bcm63xx_hsspi_ids,
409 .ops = &bcm63xx_hsspi_ops,
410 .priv_auto_alloc_size = sizeof(struct bcm63xx_hsspi_priv),
411 .child_pre_probe = bcm63xx_hsspi_child_pre_probe,
412 .probe = bcm63xx_hsspi_probe,