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[u-boot] / drivers / spi / cadence_qspi.h
1 /*
2  * Copyright (C) 2012
3  * Altera Corporation <www.altera.com>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #ifndef __CADENCE_QSPI_H__
9 #define __CADENCE_QSPI_H__
10
11 #define CQSPI_IS_ADDR(cmd_len)          (cmd_len > 1 ? 1 : 0)
12
13 #define CQSPI_NO_DECODER_MAX_CS         4
14 #define CQSPI_DECODER_MAX_CS            16
15 #define CQSPI_READ_CAPTURE_MAX_DELAY    16
16
17 struct cadence_spi_platdata {
18         unsigned int    max_hz;
19         void            *regbase;
20         void            *ahbbase;
21
22         u32             page_size;
23         u32             block_size;
24         u32             tshsl_ns;
25         u32             tsd2d_ns;
26         u32             tchsh_ns;
27         u32             tslch_ns;
28         u32             sram_size;
29 };
30
31 struct cadence_spi_priv {
32         void            *regbase;
33         void            *ahbbase;
34         size_t          cmd_len;
35         u8              cmd_buf[32];
36         size_t          data_len;
37
38         int             qspi_is_init;
39         unsigned int    qspi_calibrated_hz;
40         unsigned int    qspi_calibrated_cs;
41         unsigned int    previous_hz;
42 };
43
44 /* Functions call declaration */
45 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
46 void cadence_qspi_apb_controller_enable(void *reg_base_addr);
47 void cadence_qspi_apb_controller_disable(void *reg_base_addr);
48
49 int cadence_qspi_apb_command_read(void *reg_base_addr,
50         unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
51 int cadence_qspi_apb_command_write(void *reg_base_addr,
52         unsigned int cmdlen, const u8 *cmdbuf,
53         unsigned int txlen,  const u8 *txbuf);
54
55 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
56         unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf);
57 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
58         unsigned int rxlen, u8 *rxbuf);
59 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
60         unsigned int cmdlen, const u8 *cmdbuf);
61 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
62         unsigned int txlen, const u8 *txbuf);
63
64 void cadence_qspi_apb_chipselect(void *reg_base,
65         unsigned int chip_select, unsigned int decoder_enable);
66 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
67 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
68         unsigned int ref_clk_hz, unsigned int sclk_hz);
69 void cadence_qspi_apb_delay(void *reg_base,
70         unsigned int ref_clk, unsigned int sclk_hz,
71         unsigned int tshsl_ns, unsigned int tsd2d_ns,
72         unsigned int tchsh_ns, unsigned int tslch_ns);
73 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
74 void cadence_qspi_apb_readdata_capture(void *reg_base,
75         unsigned int bypass, unsigned int delay);
76
77 #endif /* __CADENCE_QSPI_H__ */