2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * Freescale Quad Serial Peripheral Interface (QSPI) driver
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/sizes.h>
16 #define RX_BUFFER_SIZE 0x80
17 #define TX_BUFFER_SIZE 0x40
19 #define OFFSET_BITS_MASK 0x00ffffff
21 #define FLASH_STATUS_WEL 0x02
25 #define SEQID_FAST_READ 2
28 #define SEQID_CHIP_ERASE 5
33 #define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */
34 #define QSPI_CMD_RDSR 0x05 /* Read status register */
35 #define QSPI_CMD_WREN 0x06 /* Write enable */
36 #define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */
37 #define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */
38 #define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */
39 #define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */
41 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
42 #define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
43 #define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */
44 #define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */
46 #ifdef CONFIG_SYS_FSL_QSPI_LE
47 #define qspi_read32 in_le32
48 #define qspi_write32 out_le32
49 #elif defined(CONFIG_SYS_FSL_QSPI_BE)
50 #define qspi_read32 in_be32
51 #define qspi_write32 out_be32
54 static unsigned long spi_bases[] = {
58 static unsigned long amba_bases[] = {
63 struct spi_slave slave;
64 unsigned long reg_base;
65 unsigned long amba_base;
70 /* QSPI support swapping the flash read/write data
71 * in hardware for LS102xA, but not for VF610 */
72 static inline u32 qspi_endian_xchg(u32 data)
81 static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
83 return container_of(slave, struct fsl_qspi, slave);
86 static void qspi_set_lut(struct fsl_qspi *qspi)
88 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
92 qspi_write32(®s->lutkey, LUT_KEY_VALUE);
93 qspi_write32(®s->lckcr, QSPI_LCKCR_UNLOCK);
96 lut_base = SEQID_WREN * 4;
97 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
98 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
99 qspi_write32(®s->lut[lut_base + 1], 0);
100 qspi_write32(®s->lut[lut_base + 2], 0);
101 qspi_write32(®s->lut[lut_base + 3], 0);
104 lut_base = SEQID_FAST_READ * 4;
105 if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
106 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_FAST_READ) |
107 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
108 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
110 qspi_write32(®s->lut[lut_base],
111 OPRND0(QSPI_CMD_FAST_READ_4B) |
112 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
113 OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
115 qspi_write32(®s->lut[lut_base + 1], OPRND0(8) | PAD0(LUT_PAD1) |
116 INSTR0(LUT_DUMMY) | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
118 qspi_write32(®s->lut[lut_base + 2], 0);
119 qspi_write32(®s->lut[lut_base + 3], 0);
122 lut_base = SEQID_RDSR * 4;
123 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
124 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
125 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
126 qspi_write32(®s->lut[lut_base + 1], 0);
127 qspi_write32(®s->lut[lut_base + 2], 0);
128 qspi_write32(®s->lut[lut_base + 3], 0);
131 lut_base = SEQID_SE * 4;
132 if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
133 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_SE) |
134 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
135 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
137 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_SE_4B) |
138 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
139 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
140 qspi_write32(®s->lut[lut_base + 1], 0);
141 qspi_write32(®s->lut[lut_base + 2], 0);
142 qspi_write32(®s->lut[lut_base + 3], 0);
144 /* Erase the whole chip */
145 lut_base = SEQID_CHIP_ERASE * 4;
146 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_CHIP_ERASE) |
147 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
148 qspi_write32(®s->lut[lut_base + 1], 0);
149 qspi_write32(®s->lut[lut_base + 2], 0);
150 qspi_write32(®s->lut[lut_base + 3], 0);
153 lut_base = SEQID_PP * 4;
154 if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
155 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_PP) |
156 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
157 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
159 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_PP_4B) |
160 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
161 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
162 qspi_write32(®s->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) |
163 PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
164 qspi_write32(®s->lut[lut_base + 2], 0);
165 qspi_write32(®s->lut[lut_base + 3], 0);
168 lut_base = SEQID_RDID * 4;
169 qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
170 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
171 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
172 qspi_write32(®s->lut[lut_base + 1], 0);
173 qspi_write32(®s->lut[lut_base + 2], 0);
174 qspi_write32(®s->lut[lut_base + 3], 0);
177 qspi_write32(®s->lutkey, LUT_KEY_VALUE);
178 qspi_write32(®s->lckcr, QSPI_LCKCR_LOCK);
186 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
187 unsigned int max_hz, unsigned int mode)
189 struct fsl_qspi *qspi;
190 struct fsl_qspi_regs *regs;
191 u32 reg_val, smpr_val;
192 u32 total_size, seq_id;
194 if (bus >= ARRAY_SIZE(spi_bases))
197 if (cs >= FSL_QSPI_FLASH_NUM)
200 qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
204 qspi->reg_base = spi_bases[bus];
206 * According cs, use different amba_base to choose the
207 * corresponding flash devices.
209 * If not, only one flash device is used even if passing
210 * different cs using `sf probe`
212 qspi->amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;
214 qspi->slave.max_write_size = TX_BUFFER_SIZE;
216 regs = (struct fsl_qspi_regs *)qspi->reg_base;
217 qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK);
219 smpr_val = qspi_read32(®s->smpr);
220 qspi_write32(®s->smpr, smpr_val & ~(QSPI_SMPR_FSDLY_MASK |
221 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK));
222 qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK);
224 total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
226 * Any read access to non-implemented addresses will provide
229 * In case single die flash devices, TOP_ADDR_MEMA2 and
230 * TOP_ADDR_MEMB2 should be initialized/programmed to
231 * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
232 * setting the size of these devices to 0. This would ensure
233 * that the complete memory map is assigned to only one flash device.
235 qspi_write32(®s->sfa1ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
236 qspi_write32(®s->sfa2ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
237 qspi_write32(®s->sfb1ad, total_size | amba_bases[bus]);
238 qspi_write32(®s->sfb2ad, total_size | amba_bases[bus]);
242 smpr_val = qspi_read32(®s->smpr);
243 smpr_val &= ~QSPI_SMPR_DDRSMP_MASK;
244 qspi_write32(®s->smpr, smpr_val);
245 qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK);
248 reg_val = qspi_read32(®s->bfgencr);
249 reg_val &= ~QSPI_BFGENCR_SEQID_MASK;
250 reg_val |= (seq_id << QSPI_BFGENCR_SEQID_SHIFT);
251 reg_val &= ~QSPI_BFGENCR_PAR_EN_MASK;
252 qspi_write32(®s->bfgencr, reg_val);
257 void spi_free_slave(struct spi_slave *slave)
259 struct fsl_qspi *qspi = to_qspi_spi(slave);
264 int spi_claim_bus(struct spi_slave *slave)
269 static void qspi_op_rdid(struct fsl_qspi *qspi, u32 *rxbuf, u32 len)
271 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
272 u32 mcr_reg, rbsr_reg, data;
275 mcr_reg = qspi_read32(®s->mcr);
276 qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
277 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
278 qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
280 qspi_write32(®s->sfar, qspi->amba_base);
282 qspi_write32(®s->ipcr, (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
283 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
288 while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
289 rbsr_reg = qspi_read32(®s->rbsr);
290 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
291 data = qspi_read32(®s->rbdr[i]);
292 data = qspi_endian_xchg(data);
293 memcpy(rxbuf, &data, 4);
300 qspi_write32(®s->mcr, mcr_reg);
303 static void qspi_op_read(struct fsl_qspi *qspi, u32 *rxbuf, u32 len)
305 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
310 mcr_reg = qspi_read32(®s->mcr);
311 qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
312 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
313 qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
315 to_or_from = qspi->sf_addr + qspi->amba_base;
318 qspi_write32(®s->sfar, to_or_from);
320 size = (len > RX_BUFFER_SIZE) ?
321 RX_BUFFER_SIZE : len;
323 qspi_write32(®s->ipcr,
324 (SEQID_FAST_READ << QSPI_IPCR_SEQID_SHIFT) | size);
325 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
332 while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
333 data = qspi_read32(®s->rbdr[i]);
334 data = qspi_endian_xchg(data);
335 memcpy(rxbuf, &data, 4);
340 qspi_write32(®s->mcr, qspi_read32(®s->mcr) |
341 QSPI_MCR_CLR_RXF_MASK);
344 qspi_write32(®s->mcr, mcr_reg);
347 static void qspi_op_pp(struct fsl_qspi *qspi, u32 *txbuf, u32 len)
349 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
350 u32 mcr_reg, data, reg, status_reg;
351 int i, size, tx_size;
354 mcr_reg = qspi_read32(®s->mcr);
355 qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
356 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
357 qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
360 while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
361 qspi_write32(®s->ipcr,
362 (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
363 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
366 qspi_write32(®s->ipcr,
367 (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
368 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
371 reg = qspi_read32(®s->rbsr);
372 if (reg & QSPI_RBSR_RDBFL_MASK) {
373 status_reg = qspi_read32(®s->rbdr[0]);
374 status_reg = qspi_endian_xchg(status_reg);
376 qspi_write32(®s->mcr,
377 qspi_read32(®s->mcr) | QSPI_MCR_CLR_RXF_MASK);
380 to_or_from = qspi->sf_addr + qspi->amba_base;
381 qspi_write32(®s->sfar, to_or_from);
383 tx_size = (len > TX_BUFFER_SIZE) ?
384 TX_BUFFER_SIZE : len;
386 size = (tx_size + 3) / 4;
388 for (i = 0; i < size; i++) {
389 data = qspi_endian_xchg(*txbuf);
390 qspi_write32(®s->tbdr, data);
394 qspi_write32(®s->ipcr,
395 (SEQID_PP << QSPI_IPCR_SEQID_SHIFT) | tx_size);
396 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
399 qspi_write32(®s->mcr, mcr_reg);
402 static void qspi_op_rdsr(struct fsl_qspi *qspi, u32 *rxbuf)
404 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
405 u32 mcr_reg, reg, data;
407 mcr_reg = qspi_read32(®s->mcr);
408 qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
409 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
410 qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
412 qspi_write32(®s->sfar, qspi->amba_base);
414 qspi_write32(®s->ipcr,
415 (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
416 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
420 reg = qspi_read32(®s->rbsr);
421 if (reg & QSPI_RBSR_RDBFL_MASK) {
422 data = qspi_read32(®s->rbdr[0]);
423 data = qspi_endian_xchg(data);
424 memcpy(rxbuf, &data, 4);
425 qspi_write32(®s->mcr, qspi_read32(®s->mcr) |
426 QSPI_MCR_CLR_RXF_MASK);
431 qspi_write32(®s->mcr, mcr_reg);
434 static void qspi_op_se(struct fsl_qspi *qspi)
436 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
440 mcr_reg = qspi_read32(®s->mcr);
441 qspi_write32(®s->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
442 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
443 qspi_write32(®s->rbct, QSPI_RBCT_RXBRD_USEIPS);
445 to_or_from = qspi->sf_addr + qspi->amba_base;
446 qspi_write32(®s->sfar, to_or_from);
448 qspi_write32(®s->ipcr,
449 (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
450 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
453 qspi_write32(®s->ipcr,
454 (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
455 while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
458 qspi_write32(®s->mcr, mcr_reg);
461 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
462 const void *dout, void *din, unsigned long flags)
464 struct fsl_qspi *qspi = to_qspi_spi(slave);
465 u32 bytes = DIV_ROUND_UP(bitlen, 8);
466 static u32 pp_sfaddr;
470 memcpy(&txbuf, dout, 4);
471 qspi->cur_seqid = *(u8 *)dout;
473 if (flags == SPI_XFER_END) {
474 qspi->sf_addr = pp_sfaddr;
475 qspi_op_pp(qspi, (u32 *)dout, bytes);
479 if (qspi->cur_seqid == QSPI_CMD_FAST_READ) {
480 qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
481 } else if (qspi->cur_seqid == QSPI_CMD_SE) {
482 qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
484 } else if (qspi->cur_seqid == QSPI_CMD_PP) {
485 pp_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
490 if (qspi->cur_seqid == QSPI_CMD_FAST_READ)
491 qspi_op_read(qspi, din, bytes);
492 else if (qspi->cur_seqid == QSPI_CMD_RDID)
493 qspi_op_rdid(qspi, din, bytes);
494 else if (qspi->cur_seqid == QSPI_CMD_RDSR)
495 qspi_op_rdsr(qspi, din);
501 void spi_release_bus(struct spi_slave *slave)