2 * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
3 * With help from the common/soft_spi and cpu/mpc8260 drivers
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/mpc8xxx_spi.h>
28 #ifdef CONFIG_HARD_SPI
30 #define SPI_EV_NE 0x80000000 >> 22 /* Receiver Not Empty */
31 #define SPI_EV_NF 0x80000000 >> 23 /* Transmitter Not Full */
33 #define SPI_MODE_LOOP 0x80000000 >> 1 /* Loopback mode */
34 #define SPI_MODE_REV 0x80000000 >> 5 /* Reverse mode - MSB first */
35 #define SPI_MODE_MS 0x80000000 >> 6 /* Always master */
36 #define SPI_MODE_EN 0x80000000 >> 7 /* Enable interface */
38 #define SPI_PRESCALER(reg, div) (reg)=((reg) & 0xfff0ffff) | ((div)<<16)
39 #define SPI_CHARLENGTH(reg, div) (reg)=((reg) & 0xff0fffff) | ((div)<<20)
41 #define SPI_TIMEOUT 1000
45 volatile spi8xxx_t *spi = &((immap_t *) (CFG_IMMR))->spi;
47 /* ------------------------------------------------
48 * SPI pins on the MPC83xx are not muxed, so all we do is initialize
50 * ------------------------------------------------ */
51 spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
52 SPI_PRESCALER(spi->mode, 1); /* Use SYSCLK / 8 (16.67MHz typ.) */
53 spi->event = 0xffffffff; /* Clear all SPI events */
54 spi->mask = 0x00000000; /* Mask all SPI interrupts */
55 spi->com = 0; /* LST bit doesn't do anything, so disregard */
58 int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar * dout, uchar * din)
60 volatile spi8xxx_t *spi = &((immap_t *) (CFG_IMMR))->spi;
61 unsigned int tmpdout, tmpdin, event;
62 int numBlks = bitlen / 32 + (bitlen % 32 ? 1 : 0);
64 unsigned char charSize = 32;
66 debug("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n",
67 (int)chipsel, *(uint *) dout, *(uint *) din, bitlen);
70 (*chipsel) (1); /* select the target chip */
72 spi->event = 0xffffffff; /* Clear all SPI events */
74 /* handle data in 32-bit chunks */
77 charSize = (bitlen >= 32 ? 32 : bitlen);
79 /* Shift data so it's msb-justified */
80 tmpdout = *(u32 *) dout >> (32 - charSize);
82 /* The LEN field of the SPMODE register is set as follows:
91 SPI_CHARLENGTH(spi->mode, bitlen <= 4 ? 3 : bitlen - 1);
93 SPI_CHARLENGTH(spi->mode, 0);
94 /* Set up the next iteration if sending > 32 bits */
99 spi->tx = tmpdout; /* Write the data out */
100 debug("*** spi_xfer: ... %08x written\n", tmpdout);
102 /* --------------------------------
103 * Wait for SPI transmit to get out
104 * or time out (1 second = 1000 ms)
105 * The NE event must be read and cleared first
106 * -------------------------------- */
107 for (tm = 0, isRead = 0; tm < SPI_TIMEOUT; ++tm) {
109 if (event & SPI_EV_NE) {
111 spi->event |= SPI_EV_NE;
114 *(u32 *) din = (tmpdin << (32 - charSize));
115 if (charSize == 32) {
116 /* Advance output buffer by 32 bits */
120 /* Only bail when we've had both NE and NF events.
121 * This will cause timeouts on RO devices, so maybe
122 * in the future put an arbitrary delay after writing
123 * the device. Arbitrary delays suck, though... */
124 if (isRead && (event & SPI_EV_NF))
127 if (tm >= SPI_TIMEOUT)
128 puts("*** spi_xfer: Time out during SPI transfer");
130 debug("*** spi_xfer: transfer ended. Value=%08x\n", tmpdin);
134 (*chipsel) (0); /* deselect the target chip */
138 #endif /* CONFIG_HARD_SPI */