2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/errno.h>
29 /* i.MX27 has a completely wrong register layout and register definitions in the
30 * datasheet, the correct one is in the Freescale's Linux driver */
32 #error "i.MX27 CSPI not supported due to drastic differences in register definisions" \
33 "See linux mxc_spi driver from Freescale for details."
35 #elif defined(CONFIG_MX31)
37 #include <asm/arch/mx31.h>
39 #define MXC_CSPIRXDATA 0x00
40 #define MXC_CSPITXDATA 0x04
41 #define MXC_CSPICTRL 0x08
42 #define MXC_CSPIINT 0x0C
43 #define MXC_CSPIDMA 0x10
44 #define MXC_CSPISTAT 0x14
45 #define MXC_CSPIPERIOD 0x18
46 #define MXC_CSPITEST 0x1C
47 #define MXC_CSPIRESET 0x00
49 #define MXC_CSPICTRL_EN (1 << 0)
50 #define MXC_CSPICTRL_MODE (1 << 1)
51 #define MXC_CSPICTRL_XCH (1 << 2)
52 #define MXC_CSPICTRL_SMC (1 << 3)
53 #define MXC_CSPICTRL_POL (1 << 4)
54 #define MXC_CSPICTRL_PHA (1 << 5)
55 #define MXC_CSPICTRL_SSCTL (1 << 6)
56 #define MXC_CSPICTRL_SSPOL (1 << 7)
57 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
58 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
59 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
60 #define MXC_CSPICTRL_TC (1 << 8)
61 #define MXC_CSPICTRL_RXOVF (1 << 6)
62 #define MXC_CSPICTRL_MAXBITS 0x1f
64 #define MXC_CSPIPERIOD_32KHZ (1 << 15)
65 #define MAX_SPI_BYTES 4
67 static unsigned long spi_bases[] = {
73 #define mxc_get_clock(x) mx31_get_ipg_clk()
75 #elif defined(CONFIG_MX51)
76 #include <asm/arch/imx-regs.h>
77 #include <asm/arch/clock.h>
79 #define MXC_CSPIRXDATA 0x00
80 #define MXC_CSPITXDATA 0x04
81 #define MXC_CSPICTRL 0x08
82 #define MXC_CSPICON 0x0C
83 #define MXC_CSPIINT 0x10
84 #define MXC_CSPIDMA 0x14
85 #define MXC_CSPISTAT 0x18
86 #define MXC_CSPIPERIOD 0x1C
87 #define MXC_CSPIRESET 0x00
88 #define MXC_CSPICTRL_EN (1 << 0)
89 #define MXC_CSPICTRL_MODE (1 << 1)
90 #define MXC_CSPICTRL_XCH (1 << 2)
91 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
92 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
93 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
94 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
95 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
96 #define MXC_CSPICTRL_MAXBITS 0xfff
97 #define MXC_CSPICTRL_TC (1 << 7)
98 #define MXC_CSPICTRL_RXOVF (1 << 6)
100 #define MXC_CSPIPERIOD_32KHZ (1 << 15)
101 #define MAX_SPI_BYTES 32
103 /* Bit position inside CTRL register to be associated with SS */
104 #define MXC_CSPICTRL_CHAN 18
106 /* Bit position inside CON register to be associated with SS */
107 #define MXC_CSPICON_POL 4
108 #define MXC_CSPICON_PHA 0
109 #define MXC_CSPICON_SSPOL 12
111 static unsigned long spi_bases[] = {
117 #elif defined(CONFIG_MX35)
119 #include <asm/arch/imx-regs.h>
120 #include <asm/arch/clock.h>
122 #define MXC_CSPIRXDATA 0x00
123 #define MXC_CSPITXDATA 0x04
124 #define MXC_CSPICTRL 0x08
125 #define MXC_CSPIINT 0x0C
126 #define MXC_CSPIDMA 0x10
127 #define MXC_CSPISTAT 0x14
128 #define MXC_CSPIPERIOD 0x18
129 #define MXC_CSPITEST 0x1C
130 #define MXC_CSPIRESET 0x00
132 #define MXC_CSPICTRL_EN (1 << 0)
133 #define MXC_CSPICTRL_MODE (1 << 1)
134 #define MXC_CSPICTRL_XCH (1 << 2)
135 #define MXC_CSPICTRL_SMC (1 << 3)
136 #define MXC_CSPICTRL_POL (1 << 4)
137 #define MXC_CSPICTRL_PHA (1 << 5)
138 #define MXC_CSPICTRL_SSCTL (1 << 6)
139 #define MXC_CSPICTRL_SSPOL (1 << 7)
140 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
141 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
142 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
143 #define MXC_CSPICTRL_TC (1 << 7)
144 #define MXC_CSPICTRL_RXOVF (1 << 6)
145 #define MXC_CSPICTRL_MAXBITS 0xfff
147 #define MXC_CSPIPERIOD_32KHZ (1 << 15)
148 #define MAX_SPI_BYTES 4
150 static unsigned long spi_bases[] = {
156 #error "Unsupported architecture"
159 #define OUT MXC_GPIO_DIRECTION_OUT
161 struct mxc_spi_slave {
162 struct spi_slave slave;
165 #if defined(CONFIG_MX51)
172 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
174 return container_of(slave, struct mxc_spi_slave, slave);
177 static inline u32 reg_read(unsigned long addr)
179 return *(volatile unsigned long*)addr;
182 static inline void reg_write(unsigned long addr, u32 val)
184 *(volatile unsigned long*)addr = val;
187 void spi_cs_activate(struct spi_slave *slave)
189 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
191 mxc_gpio_set(mxcs->gpio, mxcs->ss_pol);
194 void spi_cs_deactivate(struct spi_slave *slave)
196 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
198 mxc_gpio_set(mxcs->gpio,
202 u32 get_cspi_div(u32 div)
206 for (i = 0; i < 8; i++) {
213 #if defined(CONFIG_MX31) || defined(CONFIG_MX35)
214 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
215 unsigned int max_hz, unsigned int mode)
217 unsigned int ctrl_reg;
221 clk_src = mxc_get_clock(MXC_CSPI_CLK);
223 div = clk_src / max_hz;
224 div = get_cspi_div(div);
226 debug("clk %d Hz, div %d, real clk %d Hz\n",
227 max_hz, div, clk_src / (4 << div));
229 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
230 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
231 MXC_CSPICTRL_DATARATE(div) |
239 ctrl_reg |= MXC_CSPICTRL_PHA;
241 ctrl_reg |= MXC_CSPICTRL_POL;
242 if (mode & SPI_CS_HIGH)
243 ctrl_reg |= MXC_CSPICTRL_SSPOL;
244 mxcs->ctrl_reg = ctrl_reg;
250 #if defined(CONFIG_MX51)
251 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
252 unsigned int max_hz, unsigned int mode)
254 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
255 s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config;
256 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
259 printf("Error: desired clock is 0\n");
263 reg_ctrl = reg_read(mxcs->base + MXC_CSPICTRL);
266 reg_write(mxcs->base + MXC_CSPICTRL, 0);
267 reg_write(mxcs->base + MXC_CSPICTRL, (reg_ctrl | 0x1));
270 * The following computation is taken directly from Freescale's code.
272 if (clk_src > max_hz) {
273 pre_div = clk_src / max_hz;
275 post_div = pre_div / 16;
279 for (i = 0; i < 16; i++) {
280 if ((1 << i) >= post_div)
284 printf("Error: no divider for the freq: %d\n",
292 debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
293 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
294 MXC_CSPICTRL_SELCHAN(cs);
295 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
296 MXC_CSPICTRL_PREDIV(pre_div);
297 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
298 MXC_CSPICTRL_POSTDIV(post_div);
300 /* always set to master mode */
301 reg_ctrl |= 1 << (cs + 4);
303 /* We need to disable SPI before changing registers */
304 reg_ctrl &= ~MXC_CSPICTRL_EN;
306 if (mode & SPI_CS_HIGH)
315 reg_config = reg_read(mxcs->base + MXC_CSPICON);
318 * Configuration register setup
319 * The MX51 supports different setup for each SS
321 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
322 (ss_pol << (cs + MXC_CSPICON_SSPOL));
323 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
324 (sclkpol << (cs + MXC_CSPICON_POL));
325 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
326 (sclkpha << (cs + MXC_CSPICON_PHA));
328 debug("reg_ctrl = 0x%x\n", reg_ctrl);
329 reg_write(mxcs->base + MXC_CSPICTRL, reg_ctrl);
330 debug("reg_config = 0x%x\n", reg_config);
331 reg_write(mxcs->base + MXC_CSPICON, reg_config);
333 /* save config register and control register */
334 mxcs->ctrl_reg = reg_ctrl;
335 mxcs->cfg_reg = reg_config;
337 /* clear interrupt reg */
338 reg_write(mxcs->base + MXC_CSPIINT, 0);
339 reg_write(mxcs->base + MXC_CSPISTAT,
340 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
346 int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
347 const u8 *dout, u8 *din, unsigned long flags)
349 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
350 int nbytes = (bitlen + 7) / 8;
353 debug("%s: bitlen %d dout 0x%x din 0x%x\n",
354 __func__, bitlen, (u32)dout, (u32)din);
356 mxcs->ctrl_reg = (mxcs->ctrl_reg &
357 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
358 MXC_CSPICTRL_BITCOUNT(bitlen - 1);
360 reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
362 reg_write(mxcs->base + MXC_CSPICON, mxcs->cfg_reg);
365 /* Clear interrupt register */
366 reg_write(mxcs->base + MXC_CSPISTAT,
367 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
370 * The SPI controller works only with words,
371 * check if less than a word is sent.
372 * Access to the FIFO is only 32 bit
376 cnt = (bitlen % 32) / 8;
378 for (i = 0; i < cnt; i++) {
379 data = (data << 8) | (*dout++ & 0xFF);
382 debug("Sending SPI 0x%x\n", data);
384 reg_write(mxcs->base + MXC_CSPITXDATA, data);
393 /* Buffer is not 32-bit aligned */
394 if ((unsigned long)dout & 0x03) {
396 for (i = 0; i < 4; i++)
397 data = (data << 8) | (*dout++ & 0xFF);
400 data = cpu_to_be32(data);
404 debug("Sending SPI 0x%x\n", data);
405 reg_write(mxcs->base + MXC_CSPITXDATA, data);
409 /* FIFO is written, now starts the transfer setting the XCH bit */
410 reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg |
411 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
413 /* Wait until the TC (Transfer completed) bit is set */
414 while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0)
417 /* Transfer completed, clear any pending request */
418 reg_write(mxcs->base + MXC_CSPISTAT,
419 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
421 nbytes = (bitlen + 7) / 8;
426 data = reg_read(mxcs->base + MXC_CSPIRXDATA);
427 cnt = (bitlen % 32) / 8;
428 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
429 debug("SPI Rx unaligned: 0x%x\n", data);
431 memcpy(din, &data, cnt);
439 tmp = reg_read(mxcs->base + MXC_CSPIRXDATA);
440 data = cpu_to_be32(tmp);
441 debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
442 cnt = min(nbytes, sizeof(data));
444 memcpy(din, &data, cnt);
454 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
455 void *din, unsigned long flags)
457 int n_bytes = (bitlen + 7) / 8;
461 u8 *p_outbuf = (u8 *)dout;
462 u8 *p_inbuf = (u8 *)din;
467 if (flags & SPI_XFER_BEGIN)
468 spi_cs_activate(slave);
470 while (n_bytes > 0) {
472 if (n_bytes < MAX_SPI_BYTES)
475 blk_size = MAX_SPI_BYTES;
477 n_bits = blk_size * 8;
479 ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
484 p_outbuf += blk_size;
490 if (flags & SPI_XFER_END) {
491 spi_cs_deactivate(slave);
501 static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
506 * Some SPI devices require active chip-select over multiple
507 * transactions, we achieve this using a GPIO. Still, the SPI
508 * controller has to be configured to use one of its own chipselects.
509 * To use this feature you have to call spi_setup_slave() with
510 * cs = internal_cs | (gpio << 8), and you have to use some unused
511 * on this SPI controller cs between 0 and 3.
514 mxcs->gpio = cs >> 8;
516 ret = mxc_gpio_direction(mxcs->gpio, OUT);
518 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
528 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
529 unsigned int max_hz, unsigned int mode)
531 struct mxc_spi_slave *mxcs;
534 if (bus >= ARRAY_SIZE(spi_bases))
537 mxcs = malloc(sizeof(struct mxc_spi_slave));
539 puts("mxc_spi: SPI Slave not allocated !\n");
543 ret = decode_cs(mxcs, cs);
551 mxcs->slave.bus = bus;
553 mxcs->base = spi_bases[bus];
554 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
556 ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
558 printf("mxc_spi: cannot setup SPI controller\n");
565 void spi_free_slave(struct spi_slave *slave)
567 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
572 int spi_claim_bus(struct spi_slave *slave)
574 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
576 reg_write(mxcs->base + MXC_CSPIRESET, 1);
578 reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
579 reg_write(mxcs->base + MXC_CSPIPERIOD,
580 MXC_CSPIPERIOD_32KHZ);
581 reg_write(mxcs->base + MXC_CSPIINT, 0);
586 void spi_release_bus(struct spi_slave *slave)
588 /* TODO: Shut the controller down */