2 * spi driver for rockchip
4 * (C) Copyright 2015 Google, Inc
6 * (C) Copyright 2008-2013 Rockchip Electronics
7 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
9 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/errno.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/periph.h>
21 #include <dm/pinctrl.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 /* Change to 1 to output registers at the start of each transaction */
27 #define DEBUG_RK_SPI 0
29 struct rockchip_spi_platdata {
31 struct udevice *pinctrl;
32 s32 frequency; /* Default clock frequency, -1 for none */
34 uint deactivate_delay_us; /* Delay to wait after deactivate */
35 uint activate_delay_us; /* Delay to wait after activate */
38 struct rockchip_spi_priv {
39 struct rockchip_spi *regs;
42 unsigned int max_freq;
44 ulong last_transaction_us; /* Time of last transaction end */
45 u8 bits_per_word; /* max 16 bits per word */
47 unsigned int speed_hz;
48 unsigned int last_speed_hz;
53 #define SPI_FIFO_DEPTH 32
55 static void rkspi_dump_regs(struct rockchip_spi *regs)
57 debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0));
58 debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1));
59 debug("ssienr: \t\t0x%08x\n", readl(®s->enr));
60 debug("ser: \t\t0x%08x\n", readl(®s->ser));
61 debug("baudr: \t\t0x%08x\n", readl(®s->baudr));
62 debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr));
63 debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr));
64 debug("txflr: \t\t0x%08x\n", readl(®s->txflr));
65 debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr));
66 debug("sr: \t\t0x%08x\n", readl(®s->sr));
67 debug("imr: \t\t0x%08x\n", readl(®s->imr));
68 debug("isr: \t\t0x%08x\n", readl(®s->isr));
69 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr));
70 debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr));
71 debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr));
74 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
76 writel(enable ? 1 : 0, ®s->enr);
79 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
83 clk_div = clk_get_divisor(priv->input_rate, speed);
84 debug("spi speed %u, div %u\n", speed, clk_div);
86 writel(clk_div, &priv->regs->baudr);
87 priv->last_speed_hz = speed;
90 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
95 while (readl(®s->sr) & SR_BUSY) {
96 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
97 debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
105 static void spi_cs_activate(struct udevice *dev, uint cs)
107 struct udevice *bus = dev->parent;
108 struct rockchip_spi_platdata *plat = bus->platdata;
109 struct rockchip_spi_priv *priv = dev_get_priv(bus);
110 struct rockchip_spi *regs = priv->regs;
112 debug("activate cs%u\n", cs);
113 writel(1 << cs, ®s->ser);
114 if (plat->activate_delay_us)
115 udelay(plat->activate_delay_us);
118 static void spi_cs_deactivate(struct udevice *dev, uint cs)
120 struct udevice *bus = dev->parent;
121 struct rockchip_spi_platdata *plat = bus->platdata;
122 struct rockchip_spi_priv *priv = dev_get_priv(bus);
123 struct rockchip_spi *regs = priv->regs;
125 debug("deactivate cs%u\n", cs);
126 writel(0, ®s->ser);
128 /* Remember time of this transaction so we can honour the bus delay */
129 if (plat->deactivate_delay_us)
130 priv->last_transaction_us = timer_get_us();
133 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
135 struct rockchip_spi_platdata *plat = bus->platdata;
136 struct rockchip_spi_priv *priv = dev_get_priv(bus);
137 const void *blob = gd->fdt_blob;
138 int node = bus->of_offset;
141 plat->base = dev_get_addr(bus);
142 ret = uclass_get_device(UCLASS_PINCTRL, 0, &plat->pinctrl);
145 ret = pinctrl_get_periph_id(plat->pinctrl, bus);
148 debug("%s: Could not get peripheral ID for %s: %d\n", __func__,
152 plat->periph_id = ret;
153 ret = clk_get_by_index(bus, 0, &priv->clk);
155 debug("%s: Could not get clock for %s: %d\n", __func__,
161 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
163 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
164 "spi-deactivate-delay", 0);
165 plat->activate_delay_us = fdtdec_get_int(blob, node,
166 "spi-activate-delay", 0);
167 debug("%s: base=%x, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
168 __func__, (uint)plat->base, plat->periph_id, plat->frequency,
169 plat->deactivate_delay_us);
174 static int rockchip_spi_probe(struct udevice *bus)
176 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
177 struct rockchip_spi_priv *priv = dev_get_priv(bus);
180 debug("%s: probe\n", __func__);
181 priv->regs = (struct rockchip_spi *)plat->base;
183 priv->last_transaction_us = timer_get_us();
184 priv->max_freq = plat->frequency;
187 * Use 99 MHz as our clock since it divides nicely into 594 MHz which
188 * is the assumed speed for CLK_GENERAL.
190 ret = clk_set_periph_rate(priv->clk, priv->clk_id, 99000000);
192 debug("%s: Failed to set clock: %d\n", __func__, ret);
195 priv->input_rate = ret;
196 debug("%s: rate = %u\n", __func__, priv->input_rate);
197 priv->bits_per_word = 8;
198 priv->tmode = TMOD_TR; /* Tx & Rx */
203 static int rockchip_spi_claim_bus(struct udevice *dev)
205 struct udevice *bus = dev->parent;
206 struct rockchip_spi_priv *priv = dev_get_priv(bus);
207 struct rockchip_spi *regs = priv->regs;
210 #if !CONFIG_IS_ENABLED(PINCTRL_FULL)
211 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
212 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
216 /* Disable the SPI hardware */
217 rkspi_enable_chip(regs, 0);
219 switch (priv->bits_per_word) {
223 spi_tf = HALF_WORD_OFF;
228 spi_tf = HALF_WORD_ON;
231 debug("%s: unsupported bits: %dbits\n", __func__,
232 priv->bits_per_word);
233 return -EPROTONOSUPPORT;
236 if (priv->speed_hz != priv->last_speed_hz)
237 rkspi_set_clk(priv, priv->speed_hz);
240 ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
242 /* Data Frame Size */
243 ctrlr0 |= spi_dfs << DFS_SHIFT;
245 /* set SPI mode 0..3 */
246 if (priv->mode & SPI_CPOL)
247 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
248 if (priv->mode & SPI_CPHA)
249 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
251 /* Chip Select Mode */
252 ctrlr0 |= CSM_KEEP << CSM_SHIFT;
254 /* SSN to Sclk_out delay */
255 ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
257 /* Serial Endian Mode */
258 ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
261 ctrlr0 |= FBM_MSB << FBM_SHIFT;
263 /* Byte and Halfword Transform */
264 ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;
266 /* Rxd Sample Delay */
267 ctrlr0 |= 0 << RXDSD_SHIFT;
270 ctrlr0 |= FRF_SPI << FRF_SHIFT;
273 ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
275 writel(ctrlr0, ®s->ctrlr0);
276 #if !CONFIG_IS_ENABLED(PINCTRL_FULL)
277 ret = pinctrl_request(plat->pinctrl, plat->periph_id, slave_plat->cs);
279 debug("%s: Cannot request pinctrl: %d\n", __func__, ret);
287 static int rockchip_spi_release_bus(struct udevice *dev)
292 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
293 const void *dout, void *din, unsigned long flags)
295 struct udevice *bus = dev->parent;
296 struct rockchip_spi_priv *priv = dev_get_priv(bus);
297 struct rockchip_spi *regs = priv->regs;
298 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
299 int len = bitlen >> 3;
300 const u8 *out = dout;
305 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
308 rkspi_dump_regs(regs);
310 /* Assert CS before transfer */
311 if (flags & SPI_XFER_BEGIN)
312 spi_cs_activate(dev, slave_plat->cs);
315 int todo = min(len, 0xffff);
317 rkspi_enable_chip(regs, true);
318 writel(todo - 1, ®s->ctrlr1);
319 rkspi_enable_chip(regs, true);
323 while (toread || towrite) {
324 u32 status = readl(®s->sr);
326 if (towrite && !(status & SR_TF_FULL)) {
327 writel(out ? *out++ : 0, regs->txdr);
330 if (toread && !(status & SR_RF_EMPT)) {
331 u32 byte = readl(regs->rxdr);
338 ret = rkspi_wait_till_not_busy(regs);
344 /* Deassert CS after transfer */
345 if (flags & SPI_XFER_END)
346 spi_cs_deactivate(dev, slave_plat->cs);
348 rkspi_enable_chip(regs, false);
353 static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
355 struct rockchip_spi_priv *priv = dev_get_priv(bus);
357 if (speed > ROCKCHIP_SPI_MAX_RATE)
359 if (speed > priv->max_freq)
360 speed = priv->max_freq;
361 priv->speed_hz = speed;
366 static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
368 struct rockchip_spi_priv *priv = dev_get_priv(bus);
375 static const struct dm_spi_ops rockchip_spi_ops = {
376 .claim_bus = rockchip_spi_claim_bus,
377 .release_bus = rockchip_spi_release_bus,
378 .xfer = rockchip_spi_xfer,
379 .set_speed = rockchip_spi_set_speed,
380 .set_mode = rockchip_spi_set_mode,
382 * cs_info is not needed, since we require all chip selects to be
383 * in the device tree explicitly
387 static const struct udevice_id rockchip_spi_ids[] = {
388 { .compatible = "rockchip,rk3288-spi" },
392 U_BOOT_DRIVER(rockchip_spi) = {
393 .name = "rockchip_spi",
395 .of_match = rockchip_spi_ids,
396 .ops = &rockchip_spi_ops,
397 .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
398 .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
399 .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
400 .probe = rockchip_spi_probe,