2 * SH QSPI (Quad SPI) driver
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 * SPDX-License-Identifier: GPL-2.0
15 #include <asm/arch/rmobile.h>
18 /* SH QSPI register bit masks <REG>_<BIT> */
19 #define SPCR_MSTR 0x08
21 #define SPSR_SPRFF 0x80
22 #define SPSR_SPTEF 0x20
23 #define SPPCR_IO3FV 0x04
24 #define SPPCR_IO2FV 0x02
25 #define SPPCR_IO1FV 0x01
26 #define SPBDCR_RXBC0 BIT(0)
27 #define SPCMD_SCKDEN BIT(15)
28 #define SPCMD_SLNDEN BIT(14)
29 #define SPCMD_SPNDEN BIT(13)
30 #define SPCMD_SSLKP BIT(7)
31 #define SPCMD_BRDV0 BIT(2)
32 #define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \
33 SPCMD_SPNDEN | SPCMD_SSLKP | \
35 #define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \
37 #define SPBFCR_TXRST BIT(7)
38 #define SPBFCR_RXRST BIT(6)
39 #define SPBFCR_TXTRG 0x30
40 #define SPBFCR_RXTRG 0x07
42 /* SH QSPI register set */
70 struct sh_qspi_slave {
71 struct spi_slave slave;
72 struct sh_qspi_regs *regs;
75 static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
77 return container_of(slave, struct sh_qspi_slave, slave);
80 static void sh_qspi_init(struct sh_qspi_slave *ss)
83 /* Set master mode only */
84 writeb(SPCR_MSTR, &ss->regs->spcr);
86 /* Set SSL signal level */
87 writeb(0x00, &ss->regs->sslp);
89 /* Set MOSI signal value when transfer is in idle state */
90 writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr);
92 /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
93 writeb(0x01, &ss->regs->spbr);
95 /* Disable Dummy Data Transmission */
96 writeb(0x00, &ss->regs->spdcr);
98 /* Set clock delay value */
99 writeb(0x00, &ss->regs->spckd);
101 /* Set SSL negation delay value */
102 writeb(0x00, &ss->regs->sslnd);
104 /* Set next-access delay value */
105 writeb(0x00, &ss->regs->spnd);
107 /* Set equence command */
108 writew(SPCMD_INIT2, &ss->regs->spcmd0);
110 /* Reset transfer and receive Buffer */
111 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
113 /* Clear transfer and receive Buffer control bit */
114 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
116 /* Set equence control method. Use equence0 only */
117 writeb(0x00, &ss->regs->spscr);
119 /* Enable SPI function */
120 setbits_8(&ss->regs->spcr, SPCR_SPE);
123 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
128 void spi_cs_activate(struct spi_slave *slave)
130 struct sh_qspi_slave *ss = to_sh_qspi(slave);
132 /* Set master mode only */
133 writeb(SPCR_MSTR, &ss->regs->spcr);
136 writew(SPCMD_INIT1, &ss->regs->spcmd0);
138 /* Reset transfer and receive Buffer */
139 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
141 /* Clear transfer and receive Buffer control bit */
142 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
144 /* Set equence control method. Use equence0 only */
145 writeb(0x00, &ss->regs->spscr);
147 /* Enable SPI function */
148 setbits_8(&ss->regs->spcr, SPCR_SPE);
151 void spi_cs_deactivate(struct spi_slave *slave)
153 struct sh_qspi_slave *ss = to_sh_qspi(slave);
155 /* Disable SPI Function */
156 clrbits_8(&ss->regs->spcr, SPCR_SPE);
164 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
165 unsigned int max_hz, unsigned int mode)
167 struct sh_qspi_slave *ss;
169 if (!spi_cs_is_valid(bus, cs))
172 ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs);
174 printf("SPI_error: Fail to allocate sh_qspi_slave\n");
178 ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;
186 void spi_free_slave(struct spi_slave *slave)
188 struct sh_qspi_slave *spi = to_sh_qspi(slave);
193 int spi_claim_bus(struct spi_slave *slave)
198 void spi_release_bus(struct spi_slave *slave)
202 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
203 void *din, unsigned long flags)
205 struct sh_qspi_slave *ss = to_sh_qspi(slave);
208 u8 dtdata = 0, drdata;
209 u8 *tdata = &dtdata, *rdata = &drdata;
210 u32 *spbmul0 = &ss->regs->spbmul0;
212 if (dout == NULL && din == NULL) {
213 if (flags & SPI_XFER_END)
214 spi_cs_deactivate(slave);
219 printf("%s: bitlen is not 8bit alined %d", __func__, bitlen);
225 if (flags & SPI_XFER_BEGIN) {
226 spi_cs_activate(slave);
228 /* Set 1048576 byte */
229 writel(0x100000, spbmul0);
232 if (flags & SPI_XFER_END)
233 writel(nbyte, spbmul0);
243 * Check if there is 32 Byte chunk and if there is, transfer
244 * it in one burst, otherwise transfer on byte-by-byte basis.
246 chunk = (nbyte >= 32) ? 32 : 1;
248 clrsetbits_8(&ss->regs->spbfcr, SPBFCR_TXTRG | SPBFCR_RXTRG,
249 chunk == 32 ? SPBFCR_TXTRG | SPBFCR_RXTRG : 0);
251 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPTEF,
256 for (i = 0; i < chunk; i++) {
257 writeb(*tdata, &ss->regs->spdr);
262 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPRFF,
267 for (i = 0; i < chunk; i++) {
268 *rdata = readb(&ss->regs->spdr);
276 if (flags & SPI_XFER_END)
277 spi_cs_deactivate(slave);