4 * Copyright (C) 2013, Texas Instruments, Incorporated
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/omap.h>
15 #include <asm/omap_gpio.h>
16 #include <asm/omap_common.h>
17 #include <asm/ti-common/ti-edma3.h>
19 /* ti qpsi register bit masks */
20 #define QSPI_TIMEOUT 2000000
21 #define QSPI_FCLK 192000000
23 #define QSPI_CLK_EN BIT(31)
24 #define QSPI_CLK_DIV_MAX 0xffff
26 #define QSPI_EN_CS(n) (n << 28)
27 #define QSPI_WLEN(n) ((n-1) << 19)
28 #define QSPI_3_PIN BIT(18)
29 #define QSPI_RD_SNGL BIT(16)
30 #define QSPI_WR_SNGL (2 << 16)
31 #define QSPI_INVAL (4 << 16)
32 #define QSPI_RD_QUAD (7 << 16)
34 #define QSPI_DD(m, n) (m << (3 + n*8))
35 #define QSPI_CKPHA(n) (1 << (2 + n*8))
36 #define QSPI_CSPOL(n) (1 << (1 + n*8))
37 #define QSPI_CKPOL(n) (1 << (n*8))
39 #define QSPI_WC BIT(1)
40 #define QSPI_BUSY BIT(0)
41 #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
42 #define QSPI_XFER_DONE QSPI_WC
43 #define MM_SWITCH 0x01
44 #define MEM_CS(cs) ((cs + 1) << 8)
45 #define MEM_CS_UNSELECT 0xfffff0ff
46 #define MMAP_START_ADDR_DRA 0x5c000000
47 #define MMAP_START_ADDR_AM43x 0x30000000
48 #define CORE_CTRL_IO 0x4a002558
50 #define QSPI_CMD_READ (0x3 << 0)
51 #define QSPI_CMD_READ_QUAD (0x6b << 0)
52 #define QSPI_CMD_READ_FAST (0x0b << 0)
53 #define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8)
54 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
55 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
56 #define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
57 #define QSPI_SETUP0_READ_QUAD (0x3 << 12)
58 #define QSPI_CMD_WRITE (0x2 << 16)
59 #define QSPI_NUM_DUMMY_BITS (0x0 << 24)
61 /* ti qspi register set */
90 struct spi_slave slave;
91 struct ti_qspi_regs *base;
97 static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
99 return container_of(slave, struct ti_qspi_priv, slave);
102 static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
104 struct spi_slave *slave = &priv->slave;
107 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
108 slave->memory_map = (void *)MMAP_START_ADDR_DRA;
110 slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
113 #ifdef CONFIG_QSPI_QUAD_SUPPORT
114 memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
115 QSPI_SETUP0_NUM_D_BYTES_8_BITS |
116 QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
117 QSPI_NUM_DUMMY_BITS);
118 slave->mode_rx = SPI_RX_QUAD;
120 memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
121 QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
122 QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
126 writel(memval, &priv->base->setup0);
129 static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
131 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
134 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
139 clk_div = (QSPI_FCLK / hz) - 1;
142 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
143 &priv->base->clk_ctrl);
145 /* assign clk_div values */
148 else if (clk_div > QSPI_CLK_DIV_MAX)
149 clk_div = QSPI_CLK_DIV_MAX;
152 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
155 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
160 void spi_cs_activate(struct spi_slave *slave)
162 /* CS handled in xfer */
166 void spi_cs_deactivate(struct spi_slave *slave)
168 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
170 debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
172 writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
173 /* dummy readl to ensure bus sync */
174 readl(&qslave->base->cmd);
182 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
183 unsigned int max_hz, unsigned int mode)
185 struct ti_qspi_priv *priv;
188 gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
189 gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
192 priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
194 printf("SPI_error: Fail to allocate ti_qspi_priv\n");
198 priv->base = (struct ti_qspi_regs *)QSPI_BASE;
201 ti_spi_set_speed(&priv->slave, max_hz);
203 #ifdef CONFIG_TI_SPI_MMAP
204 ti_spi_setup_spi_register(priv);
210 void spi_free_slave(struct spi_slave *slave)
212 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
216 int spi_claim_bus(struct spi_slave *slave)
218 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
220 debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
223 if (priv->mode & SPI_CPHA)
224 priv->dc |= QSPI_CKPHA(slave->cs);
225 if (priv->mode & SPI_CPOL)
226 priv->dc |= QSPI_CKPOL(slave->cs);
227 if (priv->mode & SPI_CS_HIGH)
228 priv->dc |= QSPI_CSPOL(slave->cs);
230 writel(priv->dc, &priv->base->dc);
231 writel(0, &priv->base->cmd);
232 writel(0, &priv->base->data);
237 void spi_release_bus(struct spi_slave *slave)
239 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
241 debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
243 writel(0, &priv->base->dc);
244 writel(0, &priv->base->cmd);
245 writel(0, &priv->base->data);
248 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
249 void *din, unsigned long flags)
251 struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
252 uint words = bitlen >> 3; /* fixed 8-bit word length */
253 const uchar *txp = dout;
258 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
262 debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n",
263 slave->bus, slave->cs, bitlen, words, flags);
265 /* Setup mmap flags */
266 if (flags & SPI_XFER_MMAP) {
267 writel(MM_SWITCH, &priv->base->memswitch);
268 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
269 val = readl(CORE_CTRL_IO);
270 val |= MEM_CS(slave->cs);
271 writel(val, CORE_CTRL_IO);
274 } else if (flags & SPI_XFER_MMAP_END) {
275 writel(~MM_SWITCH, &priv->base->memswitch);
276 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
277 val = readl(CORE_CTRL_IO);
278 val &= MEM_CS_UNSELECT;
279 writel(val, CORE_CTRL_IO);
288 debug("spi_xfer: Non byte aligned SPI transfer\n");
292 /* Setup command reg */
294 priv->cmd |= QSPI_WLEN(8);
295 priv->cmd |= QSPI_EN_CS(slave->cs);
296 if (priv->mode & SPI_3WIRE)
297 priv->cmd |= QSPI_3_PIN;
300 /* FIXME: This delay is required for successfull
301 * completion of read/write/erase. Once its root
302 * caused, it will be remove from the driver.
309 debug("tx cmd %08x dc %08x data %02x\n",
310 priv->cmd | QSPI_WR_SNGL, priv->dc, *txp);
311 writel(*txp++, &priv->base->data);
312 writel(priv->cmd | QSPI_WR_SNGL,
314 status = readl(&priv->base->status);
315 timeout = QSPI_TIMEOUT;
316 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
318 printf("spi_xfer: TX timeout!\n");
321 status = readl(&priv->base->status);
323 debug("tx done, status %08x\n", status);
326 priv->cmd |= QSPI_RD_SNGL;
327 debug("rx cmd %08x dc %08x\n",
328 priv->cmd, priv->dc);
332 writel(priv->cmd, &priv->base->cmd);
333 status = readl(&priv->base->status);
334 timeout = QSPI_TIMEOUT;
335 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
337 printf("spi_xfer: RX timeout!\n");
340 status = readl(&priv->base->status);
342 *rxp++ = readl(&priv->base->data);
343 debug("rx done, status %08x, read %02x\n",
348 /* Terminate frame */
349 if (flags & SPI_XFER_END)
350 spi_cs_deactivate(slave);
355 /* TODO: control from sf layer to here through dm-spi */
356 #ifdef CONFIG_TI_EDMA3
357 void spi_flash_copy_mmap(void *data, void *offset, size_t len)
359 unsigned int addr = (unsigned int) (data);
360 unsigned int edma_slot_num = 1;
362 /* Invalidate the area, so no writeback into the RAM races with DMA */
363 invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
365 /* enable edma3 clocks */
366 enable_edma3_clocks();
368 /* Call edma3 api to do actual DMA transfer */
369 edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
371 /* disable edma3 clocks */
372 disable_edma3_clocks();
374 *((unsigned int *)offset) += len;