2 * Copyright (c) 2012 The Chromium OS Authors.
4 * TSC calibration codes are adapted from Linux kernel
5 * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
7 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/i8254.h>
17 #include <asm/ibmpc.h>
19 #include <asm/u-boot-x86.h>
21 #define MAX_NUM_FREQS 8
23 DECLARE_GLOBAL_DATA_PTR;
26 * According to Intel 64 and IA-32 System Programming Guide,
27 * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
28 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
29 * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
30 * so we need manually differentiate SoC families. This is what the
31 * field msr_plat does.
34 u8 x86_family; /* CPU family */
35 u8 x86_model; /* model */
36 /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
38 u32 freqs[MAX_NUM_FREQS];
41 static struct freq_desc freq_desc_tables[] = {
43 { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200 } },
45 { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 } },
46 /* TNG - Intel Atom processor Z3400 series */
47 { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 } },
48 /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
49 { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },
50 /* ANN - Intel Atom processor Z3500 series */
51 { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } },
53 { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } },
56 static int match_cpu(u8 family, u8 model)
60 for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
61 if ((family == freq_desc_tables[i].x86_family) &&
62 (model == freq_desc_tables[i].x86_model))
69 /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
70 #define id_to_freq(cpu_index, freq_id) \
71 (freq_desc_tables[cpu_index].freqs[freq_id])
74 * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
75 * reliable and the frequency is known (provided by HW).
77 * On these platforms PIT/HPET is generally not available so calibration won't
78 * work at all and there is no other clocksource to act as a watchdog for the
79 * TSC, so we have no other choice than to trust it.
81 * Returns the TSC frequency in MHz or 0 if HW does not provide it.
83 static unsigned long __maybe_unused cpu_mhz_from_msr(void)
85 u32 lo, hi, ratio, freq_id, freq;
89 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
92 cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
96 if (freq_desc_tables[cpu_index].msr_plat) {
97 rdmsr(MSR_PLATFORM_INFO, lo, hi);
98 ratio = (lo >> 8) & 0xff;
100 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
101 ratio = (hi >> 8) & 0x1f;
103 debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
105 if (freq_desc_tables[cpu_index].msr_plat == 2) {
106 /* TODO: Figure out how best to deal with this */
108 debug("Using frequency: %u KHz\n", freq);
110 /* Get FSB FREQ ID */
111 rdmsr(MSR_FSB_FREQ, lo, hi);
113 freq = id_to_freq(cpu_index, freq_id);
114 debug("Resolved frequency ID: %u, frequency: %u KHz\n",
118 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
119 res = freq * ratio / 1000;
120 debug("TSC runs at %lu MHz\n", res);
126 * This reads the current MSB of the PIT counter, and
127 * checks if we are running on sufficiently fast and
128 * non-virtualized hardware.
130 * Our expectations are:
132 * - the PIT is running at roughly 1.19MHz
134 * - each IO is going to take about 1us on real hardware,
135 * but we allow it to be much faster (by a factor of 10) or
136 * _slightly_ slower (ie we allow up to a 2us read+counter
137 * update - anything else implies a unacceptably slow CPU
138 * or PIT for the fast calibration to work.
140 * - with 256 PIT ticks to read the value, we have 214us to
141 * see the same MSB (and overhead like doing a single TSC
142 * read per MSB value etc).
144 * - We're doing 2 reads per loop (LSB, MSB), and we expect
145 * them each to take about a microsecond on real hardware.
146 * So we expect a count value of around 100. But we'll be
147 * generous, and accept anything over 50.
149 * - if the PIT is stuck, and we see *many* more reads, we
150 * return early (and the next caller of pit_expect_msb()
151 * then consider it a failure when they don't see the
152 * next expected value).
154 * These expectations mean that we know that we have seen the
155 * transition from one expected value to another with a fairly
156 * high accuracy, and we didn't miss any events. We can thus
157 * use the TSC value at the transitions to calculate a pretty
158 * good value for the TSC frequencty.
160 static inline int pit_verify_msb(unsigned char val)
164 return inb(0x42) == val;
167 static inline int pit_expect_msb(unsigned char val, u64 *tscp,
168 unsigned long *deltap)
171 u64 tsc = 0, prev_tsc = 0;
173 for (count = 0; count < 50000; count++) {
174 if (!pit_verify_msb(val))
179 *deltap = rdtsc() - prev_tsc;
183 * We require _some_ success, but the quality control
184 * will be based on the error terms on the TSC values.
190 * How many MSB values do we want to see? We aim for
191 * a maximum error rate of 500ppm (in practice the
192 * real error is much smaller), but refuse to spend
193 * more than 50ms on it.
195 #define MAX_QUICK_PIT_MS 50
196 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
198 static unsigned long __maybe_unused quick_pit_calibrate(void)
202 unsigned long d1, d2;
204 /* Set the Gate high, disable speaker */
205 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
208 * Counter 2, mode 0 (one-shot), binary count
210 * NOTE! Mode 2 decrements by two (and then the
211 * output is flipped each time, giving the same
212 * final output frequency as a decrement-by-one),
213 * so mode 0 is much better when looking at the
218 /* Start at 0xffff */
223 * The PIT starts counting at the next edge, so we
224 * need to delay for a microsecond. The easiest way
225 * to do that is to just read back the 16-bit counter
230 if (pit_expect_msb(0xff, &tsc, &d1)) {
231 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
232 if (!pit_expect_msb(0xff-i, &delta, &d2))
236 * Iterate until the error is less than 500 ppm
239 if (d1+d2 >= delta >> 11)
243 * Check the PIT one more time to verify that
244 * all TSC reads were stable wrt the PIT.
246 * This also guarantees serialization of the
247 * last cycle read ('d2') in pit_expect_msb.
249 if (!pit_verify_msb(0xfe - i))
254 debug("Fast TSC calibration failed\n");
259 * Ok, if we get here, then we've seen the
260 * MSB of the PIT decrement 'i' times, and the
261 * error has shrunk to less than 500 ppm.
263 * As a result, we can depend on there not being
264 * any odd delays anywhere, and the TSC reads are
265 * reliable (within the error).
267 * kHz = ticks / time-in-seconds / 1000;
268 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
269 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
271 delta *= PIT_TICK_RATE;
272 delta /= (i*256*1000);
273 debug("Fast TSC calibration using PIT\n");
277 /* Get the speed of the TSC timer in MHz */
278 unsigned notrace long get_tbclk_mhz(void)
280 return get_tbclk() / 1000000;
283 static ulong get_ms_timer(void)
285 return (get_ticks() * 1000) / get_tbclk();
288 ulong get_timer(ulong base)
290 return get_ms_timer() - base;
293 ulong notrace timer_get_us(void)
295 return get_ticks() / get_tbclk_mhz();
298 ulong timer_get_boot_us(void)
300 return timer_get_us();
303 void __udelay(unsigned long usec)
305 u64 now = get_ticks();
308 stop = now + usec * get_tbclk_mhz();
310 while ((int64_t)(stop - get_ticks()) > 0)
311 #if defined(CONFIG_QEMU) && defined(CONFIG_SMP)
313 * Add a 'pause' instruction on qemu target,
314 * to give other VCPUs a chance to run.
316 asm volatile("pause");
322 static int tsc_timer_get_count(struct udevice *dev, u64 *count)
324 u64 now_tick = rdtsc();
326 *count = now_tick - gd->arch.tsc_base;
331 static int tsc_timer_probe(struct udevice *dev)
333 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
335 gd->arch.tsc_base = rdtsc();
338 * If there is no clock frequency specified in the device tree,
339 * calibrate it by ourselves.
341 if (!uc_priv->clock_rate) {
342 unsigned long fast_calibrate;
344 fast_calibrate = cpu_mhz_from_msr();
345 if (!fast_calibrate) {
346 fast_calibrate = quick_pit_calibrate();
348 panic("TSC frequency is ZERO");
351 uc_priv->clock_rate = fast_calibrate * 1000000;
357 static const struct timer_ops tsc_timer_ops = {
358 .get_count = tsc_timer_get_count,
361 static const struct udevice_id tsc_timer_ids[] = {
362 { .compatible = "x86,tsc-timer", },
366 U_BOOT_DRIVER(tsc_timer) = {
369 .of_match = tsc_timer_ids,
370 .probe = tsc_timer_probe,
371 .ops = &tsc_timer_ops,
372 .flags = DM_FLAG_PRE_RELOC,