3 * Freescale Three Speed Ethernet Controller driver
5 * This software may be used and distributed according to the
6 * terms of the GNU Public License, Version 2, incorporated
9 * Copyright 2004 Freescale Semiconductor.
10 * (C) Copyright 2003, Motorola, Inc.
23 #if defined(CONFIG_TSEC_ENET)
27 DECLARE_GLOBAL_DATA_PTR;
31 static uint rxIdx; /* index of the current RX buffer */
32 static uint txIdx; /* index of the current TX buffer */
34 typedef volatile struct rtxbd {
35 txbd8_t txbd[TX_BUF_CNT];
36 rxbd8_t rxbd[PKTBUFSRX];
39 struct tsec_info_struct {
42 unsigned int phyregidx;
46 /* The tsec_info structure contains 3 values which the
47 * driver uses to determine how to operate a given ethernet
48 * device. The information needed is:
49 * phyaddr - The address of the PHY which is attached to
52 * flags - This variable indicates whether the device
53 * supports gigabit speed ethernet, and whether it should be
56 * phyregidx - This variable specifies which ethernet device
57 * controls the MII Management registers which are connected
58 * to the PHY. For now, only TSEC1 (index 0) has
59 * access to the PHYs, so all of the entries have "0".
61 * The values specified in the table are taken from the board's
62 * config file in include/configs/. When implementing a new
63 * board with ethernet capability, it is necessary to define:
67 * for n = 1,2,3, etc. And for FEC:
71 static struct tsec_info_struct tsec_info[] = {
72 #if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
73 {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
74 #elif defined(CONFIG_MPC86XX_TSEC1)
75 {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
79 #if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
80 {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
81 #elif defined(CONFIG_MPC86XX_TSEC2)
82 {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
86 #ifdef CONFIG_MPC85XX_FEC
87 {FEC_PHY_ADDR, 0, FEC_PHYIDX},
89 #if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3)
90 {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
94 #if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4)
95 {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
102 #define MAXCONTROLLERS (4)
104 static int relocated = 0;
106 static struct tsec_private *privlist[MAXCONTROLLERS];
109 static RTXBD rtx __attribute__ ((aligned(8)));
111 #error "rtx must be 64-bit aligned"
114 static int tsec_send(struct eth_device* dev, volatile void *packet, int length);
115 static int tsec_recv(struct eth_device* dev);
116 static int tsec_init(struct eth_device* dev, bd_t * bd);
117 static void tsec_halt(struct eth_device* dev);
118 static void init_registers(volatile tsec_t *regs);
119 static void startup_tsec(struct eth_device *dev);
120 static int init_phy(struct eth_device *dev);
121 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
122 uint read_phy_reg(struct tsec_private *priv, uint regnum);
123 struct phy_info * get_phy_info(struct eth_device *dev);
124 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
125 static void adjust_link(struct eth_device *dev);
126 static void relocate_cmds(void);
127 static int tsec_miiphy_write(char *devname, unsigned char addr,
128 unsigned char reg, unsigned short value);
129 static int tsec_miiphy_read(char *devname, unsigned char addr,
130 unsigned char reg, unsigned short *value);
132 /* Initialize device structure. Returns success if PHY
133 * initialization succeeded (i.e. if it recognizes the PHY)
135 int tsec_initialize(bd_t *bis, int index, char *devname)
137 struct eth_device* dev;
139 struct tsec_private *priv;
141 dev = (struct eth_device*) malloc(sizeof *dev);
146 memset(dev, 0, sizeof *dev);
148 priv = (struct tsec_private *) malloc(sizeof(*priv));
153 privlist[index] = priv;
154 priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index*TSEC_SIZE);
155 priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
156 tsec_info[index].phyregidx*TSEC_SIZE);
158 priv->phyaddr = tsec_info[index].phyaddr;
159 priv->flags = tsec_info[index].flags;
161 sprintf(dev->name, devname);
164 dev->init = tsec_init;
165 dev->halt = tsec_halt;
166 dev->send = tsec_send;
167 dev->recv = tsec_recv;
169 /* Tell u-boot to get the addr from the env */
171 dev->enetaddr[i] = 0;
177 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
178 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
180 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
181 && !defined(BITBANGMII)
182 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
185 /* Try to initialize PHY here, and return */
186 return init_phy(dev);
190 /* Initializes data structures and registers for the controller,
191 * and brings the interface up. Returns the link status, meaning
192 * that it returns success if the link is up, failure otherwise.
193 * This allows u-boot to find the first active controller. */
194 int tsec_init(struct eth_device* dev, bd_t * bd)
197 char tmpbuf[MAC_ADDR_LEN];
199 struct tsec_private *priv = (struct tsec_private *)dev->priv;
200 volatile tsec_t *regs = priv->regs;
202 /* Make sure the controller is stopped */
205 /* Init MACCFG2. Defaults to GMII */
206 regs->maccfg2 = MACCFG2_INIT_SETTINGS;
209 regs->ecntrl = ECNTRL_INIT_SETTINGS;
211 /* Copy the station address into the address registers.
212 * Backwards, because little endian MACS are dumb */
213 for(i=0;i<MAC_ADDR_LEN;i++) {
214 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
216 regs->macstnaddr1 = *((uint *)(tmpbuf));
218 tempval = *((uint *)(tmpbuf +4));
220 regs->macstnaddr2 = tempval;
222 /* reset the indices to zero */
226 /* Clear out (for the most part) the other registers */
227 init_registers(regs);
229 /* Ready the device for tx/rx */
232 /* If there's no link, fail */
238 /* Write value to the device's PHY through the registers
239 * specified in priv, modifying the register specified in regnum.
240 * It will wait for the write to be done (or for a timeout to
241 * expire) before exiting
243 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
245 volatile tsec_t *regbase = priv->phyregs;
246 uint phyid = priv->phyaddr;
249 regbase->miimadd = (phyid << 8) | regnum;
250 regbase->miimcon = value;
254 while((regbase->miimind & MIIMIND_BUSY) && timeout--);
258 /* Reads register regnum on the device's PHY through the
259 * registers specified in priv. It lowers and raises the read
260 * command, and waits for the data to become valid (miimind
261 * notvalid bit cleared), and the bus to cease activity (miimind
262 * busy bit cleared), and then returns the value
264 uint read_phy_reg(struct tsec_private *priv, uint regnum)
267 volatile tsec_t *regbase = priv->phyregs;
268 uint phyid = priv->phyaddr;
270 /* Put the address of the phy, and the register
271 * number into MIIMADD */
272 regbase->miimadd = (phyid << 8) | regnum;
274 /* Clear the command register, and wait */
275 regbase->miimcom = 0;
278 /* Initiate a read command, and wait */
279 regbase->miimcom = MIIM_READ_COMMAND;
282 /* Wait for the the indication that the read is done */
283 while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY)));
285 /* Grab the value read from the PHY */
286 value = regbase->miimstat;
292 /* Discover which PHY is attached to the device, and configure it
293 * properly. If the PHY is not recognized, then return 0
294 * (failure). Otherwise, return 1
296 static int init_phy(struct eth_device *dev)
298 struct tsec_private *priv = (struct tsec_private *)dev->priv;
299 struct phy_info *curphy;
301 /* Assign a Physical address to the TBI */
304 volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
305 regs->tbipa = TBIPA_VALUE;
306 regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
307 regs->tbipa = TBIPA_VALUE;
311 /* Reset MII (due to new addresses) */
312 priv->phyregs->miimcfg = MIIMCFG_RESET;
314 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
316 while(priv->phyregs->miimind & MIIMIND_BUSY);
321 /* Get the cmd structure corresponding to the attached
323 curphy = get_phy_info(dev);
326 printf("%s: No PHY found\n", dev->name);
331 priv->phyinfo = curphy;
333 phy_run_commands(priv, priv->phyinfo->config);
339 /* Returns which value to write to the control register. */
340 /* For 10/100, the value is slightly different */
341 uint mii_cr_init(uint mii_reg, struct tsec_private *priv)
343 if(priv->flags & TSEC_GIGABIT)
344 return MIIM_CONTROL_INIT;
350 /* Parse the status register for link, and then do
351 * auto-negotiation */
352 uint mii_parse_sr(uint mii_reg, struct tsec_private *priv)
355 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
357 mii_reg = read_phy_reg(priv, MIIM_STATUS);
358 if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
361 puts ("Waiting for PHY auto negotiation to complete");
362 while (!((mii_reg & PHY_BMSR_AUTN_COMP) && (mii_reg & MIIM_STATUS_LINK))) {
366 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
367 puts (" TIMEOUT !\n");
372 if ((i++ % 1000) == 0) {
375 udelay (1000); /* 1 ms */
376 mii_reg = read_phy_reg(priv, MIIM_STATUS);
380 udelay (500000); /* another 500 ms (results in faster booting) */
389 /* Parse the 88E1011's status register for speed and duplex
391 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private *priv)
395 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
397 if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
398 (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
401 puts ("Waiting for PHY realtime link");
402 while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
403 (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
407 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
408 puts (" TIMEOUT !\n");
413 if ((i++ % 1000) == 0) {
416 udelay (1000); /* 1 ms */
417 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
420 udelay (500000); /* another 500 ms (results in faster booting) */
423 if(mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
428 speed = (mii_reg &MIIM_88E1011_PHYSTAT_SPEED);
431 case MIIM_88E1011_PHYSTAT_GBIT:
434 case MIIM_88E1011_PHYSTAT_100:
445 /* Parse the cis8201's status register for speed and duplex
447 uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv)
451 if(mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
456 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
458 case MIIM_CIS8201_AUXCONSTAT_GBIT:
461 case MIIM_CIS8201_AUXCONSTAT_100:
471 /* Parse the vsc8244's status register for speed and duplex
473 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private *priv)
477 if(mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
482 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
484 case MIIM_VSC8244_AUXCONSTAT_GBIT:
487 case MIIM_VSC8244_AUXCONSTAT_100:
499 /* Parse the DM9161's status register for speed and duplex
501 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private *priv)
503 if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
508 if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
517 /* Hack to write all 4 PHYs with the LED values */
518 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private *priv)
521 volatile tsec_t *regbase = priv->phyregs;
524 for(phyid=0;phyid<4;phyid++) {
525 regbase->miimadd = (phyid << 8) | mii_reg;
526 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
530 while((regbase->miimind & MIIMIND_BUSY) && timeout--);
533 return MIIM_CIS8204_SLEDCON_INIT;
536 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private *priv)
538 if (priv->flags & TSEC_REDUCED)
539 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
541 return MIIM_CIS8204_EPHYCON_INIT;
544 /* Initialized required registers to appropriate values, zeroing
545 * those we don't care about (unless zero is bad, in which case,
546 * choose a more appropriate value) */
547 static void init_registers(volatile tsec_t *regs)
550 regs->ievent = IEVENT_INIT_CLEAR;
552 regs->imask = IMASK_INIT_CLEAR;
554 regs->hash.iaddr0 = 0;
555 regs->hash.iaddr1 = 0;
556 regs->hash.iaddr2 = 0;
557 regs->hash.iaddr3 = 0;
558 regs->hash.iaddr4 = 0;
559 regs->hash.iaddr5 = 0;
560 regs->hash.iaddr6 = 0;
561 regs->hash.iaddr7 = 0;
563 regs->hash.gaddr0 = 0;
564 regs->hash.gaddr1 = 0;
565 regs->hash.gaddr2 = 0;
566 regs->hash.gaddr3 = 0;
567 regs->hash.gaddr4 = 0;
568 regs->hash.gaddr5 = 0;
569 regs->hash.gaddr6 = 0;
570 regs->hash.gaddr7 = 0;
572 regs->rctrl = 0x00000000;
574 /* Init RMON mib registers */
575 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
577 regs->rmon.cam1 = 0xffffffff;
578 regs->rmon.cam2 = 0xffffffff;
580 regs->mrblr = MRBLR_INIT_SETTINGS;
582 regs->minflr = MINFLR_INIT_SETTINGS;
584 regs->attr = ATTR_INIT_SETTINGS;
585 regs->attreli = ATTRELI_INIT_SETTINGS;
590 /* Configure maccfg2 based on negotiated speed and duplex
591 * reported by PHY handling code */
592 static void adjust_link(struct eth_device *dev)
594 struct tsec_private *priv = (struct tsec_private *)dev->priv;
595 volatile tsec_t *regs = priv->regs;
598 if(priv->duplexity != 0)
599 regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
601 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
603 switch(priv->speed) {
605 regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
610 regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
613 /* If We're in reduced mode, we need
614 * to say whether we're 10 or 100 MB.
616 if ((priv->speed == 100)
617 && (priv->flags & TSEC_REDUCED))
618 regs->ecntrl |= ECNTRL_R100;
620 regs->ecntrl &= ~(ECNTRL_R100);
623 printf("%s: Speed was bad\n", dev->name);
627 printf("Speed: %d, %s duplex\n", priv->speed,
628 (priv->duplexity) ? "full" : "half");
631 printf("%s: No link.\n", dev->name);
636 /* Set up the buffers and their descriptors, and bring up the
638 static void startup_tsec(struct eth_device *dev)
641 struct tsec_private *priv = (struct tsec_private *)dev->priv;
642 volatile tsec_t *regs = priv->regs;
644 /* Point to the buffer descriptors */
645 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
646 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
648 /* Initialize the Rx Buffer descriptors */
649 for (i = 0; i < PKTBUFSRX; i++) {
650 rtx.rxbd[i].status = RXBD_EMPTY;
651 rtx.rxbd[i].length = 0;
652 rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i];
654 rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP;
656 /* Initialize the TX Buffer Descriptors */
657 for(i=0; i<TX_BUF_CNT; i++) {
658 rtx.txbd[i].status = 0;
659 rtx.txbd[i].length = 0;
660 rtx.txbd[i].bufPtr = 0;
662 rtx.txbd[TX_BUF_CNT -1].status |= TXBD_WRAP;
664 /* Start up the PHY */
665 phy_run_commands(priv, priv->phyinfo->startup);
668 /* Enable Transmit and Receive */
669 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
671 /* Tell the DMA it is clear to go */
672 regs->dmactrl |= DMACTRL_INIT_SETTINGS;
673 regs->tstat = TSTAT_CLEAR_THALT;
674 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
677 /* This returns the status bits of the device. The return value
678 * is never checked, and this is what the 8260 driver did, so we
679 * do the same. Presumably, this would be zero if there were no
681 static int tsec_send(struct eth_device* dev, volatile void *packet, int length)
685 struct tsec_private *priv = (struct tsec_private *)dev->priv;
686 volatile tsec_t *regs = priv->regs;
688 /* Find an empty buffer descriptor */
689 for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
690 if (i >= TOUT_LOOP) {
691 debug ("%s: tsec: tx buffers full\n", dev->name);
696 rtx.txbd[txIdx].bufPtr = (uint)packet;
697 rtx.txbd[txIdx].length = length;
698 rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
700 /* Tell the DMA to go */
701 regs->tstat = TSTAT_CLEAR_THALT;
703 /* Wait for buffer to be transmitted */
704 for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
705 if (i >= TOUT_LOOP) {
706 debug ("%s: tsec: tx error\n", dev->name);
711 txIdx = (txIdx + 1) % TX_BUF_CNT;
712 result = rtx.txbd[txIdx].status & TXBD_STATS;
717 static int tsec_recv(struct eth_device* dev)
720 struct tsec_private *priv = (struct tsec_private *)dev->priv;
721 volatile tsec_t *regs = priv->regs;
723 while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
725 length = rtx.rxbd[rxIdx].length;
727 /* Send the packet up if there were no errors */
728 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
729 NetReceive(NetRxPackets[rxIdx], length - 4);
731 printf("Got error %x\n",
732 (rtx.rxbd[rxIdx].status & RXBD_STATS));
735 rtx.rxbd[rxIdx].length = 0;
737 /* Set the wrap bit if this is the last element in the list */
738 rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
740 rxIdx = (rxIdx + 1) % PKTBUFSRX;
743 if(regs->ievent&IEVENT_BSY) {
744 regs->ievent = IEVENT_BSY;
745 regs->rstat = RSTAT_CLEAR_RHALT;
753 /* Stop the interface */
754 static void tsec_halt(struct eth_device* dev)
756 struct tsec_private *priv = (struct tsec_private *)dev->priv;
757 volatile tsec_t *regs = priv->regs;
759 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
760 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
762 while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)));
764 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
766 /* Shut down the PHY, as needed */
767 phy_run_commands(priv, priv->phyinfo->shutdown);
771 struct phy_info phy_info_M88E1011S = {
775 (struct phy_cmd[]) { /* config */
776 /* Reset and configure the PHY */
777 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
779 {0x1e, 0x200c, NULL},
783 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
784 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
785 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
786 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
789 (struct phy_cmd[]) { /* startup */
790 /* Status is read once to clear old link state */
791 {MIIM_STATUS, miim_read, NULL},
793 {MIIM_STATUS, miim_read, &mii_parse_sr},
794 /* Read the status */
795 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
798 (struct phy_cmd[]) { /* shutdown */
803 struct phy_info phy_info_M88E1111S = {
807 (struct phy_cmd[]) { /* config */
808 /* Reset and configure the PHY */
809 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
811 {0x1e, 0x200c, NULL},
815 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
816 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
817 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
818 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
821 (struct phy_cmd[]) { /* startup */
822 /* Status is read once to clear old link state */
823 {MIIM_STATUS, miim_read, NULL},
825 {MIIM_STATUS, miim_read, &mii_parse_sr},
826 /* Read the status */
827 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
830 (struct phy_cmd[]) { /* shutdown */
835 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
838 uint mii_data = read_phy_reg(priv, mii_reg);
841 /* Setting MIIM_88E1145_PHY_EXT_CR */
842 if (priv->flags & TSEC_REDUCED)
844 MIIM_M88E1145_RGMII_RX_DELAY |
845 MIIM_M88E1145_RGMII_TX_DELAY;
850 static struct phy_info phy_info_M88E1145 = {
854 (struct phy_cmd[]) { /* config */
861 /* Reset and configure the PHY */
862 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
863 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
864 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
865 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL},
866 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
867 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
868 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
871 (struct phy_cmd[]) { /* startup */
872 /* Status is read once to clear old link state */
873 {MIIM_STATUS, miim_read, NULL},
875 {MIIM_STATUS, miim_read, &mii_parse_sr},
876 {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL},
877 /* Read the Status */
878 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
881 (struct phy_cmd[]) { /* shutdown */
887 struct phy_info phy_info_cis8204 = {
891 (struct phy_cmd[]) { /* config */
892 /* Override PHY config settings */
893 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
894 /* Configure some basic stuff */
895 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
896 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, &mii_cis8204_fixled},
897 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, &mii_cis8204_setmode},
900 (struct phy_cmd[]) { /* startup */
901 /* Read the Status (2x to make sure link is right) */
902 {MIIM_STATUS, miim_read, NULL},
904 {MIIM_STATUS, miim_read, &mii_parse_sr},
905 /* Read the status */
906 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
909 (struct phy_cmd[]) { /* shutdown */
915 struct phy_info phy_info_cis8201 = {
919 (struct phy_cmd[]) { /* config */
920 /* Override PHY config settings */
921 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
922 /* Set up the interface mode */
923 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
924 /* Configure some basic stuff */
925 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
928 (struct phy_cmd[]) { /* startup */
929 /* Read the Status (2x to make sure link is right) */
930 {MIIM_STATUS, miim_read, NULL},
932 {MIIM_STATUS, miim_read, &mii_parse_sr},
933 /* Read the status */
934 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
937 (struct phy_cmd[]) { /* shutdown */
941 struct phy_info phy_info_VSC8244 = {
945 (struct phy_cmd[]) { /* config */
946 /* Override PHY config settings */
947 /* Configure some basic stuff */
948 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
951 (struct phy_cmd[]) { /* startup */
952 /* Read the Status (2x to make sure link is right) */
953 {MIIM_STATUS, miim_read, NULL},
955 {MIIM_STATUS, miim_read, &mii_parse_sr},
956 /* Read the status */
957 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
960 (struct phy_cmd[]) { /* shutdown */
966 struct phy_info phy_info_dm9161 = {
970 (struct phy_cmd[]) { /* config */
971 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
972 /* Do not bypass the scrambler/descrambler */
973 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
974 /* Clear 10BTCSR to default */
975 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL},
976 /* Configure some basic stuff */
977 {MIIM_CONTROL, MIIM_CR_INIT, NULL},
978 /* Restart Auto Negotiation */
979 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
982 (struct phy_cmd[]) { /* startup */
983 /* Status is read once to clear old link state */
984 {MIIM_STATUS, miim_read, NULL},
986 {MIIM_STATUS, miim_read, &mii_parse_sr},
987 /* Read the status */
988 {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr},
991 (struct phy_cmd[]) { /* shutdown */
996 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1000 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1003 case MIIM_LXT971_SR2_10HDX:
1005 priv->duplexity = 0;
1007 case MIIM_LXT971_SR2_10FDX:
1009 priv->duplexity = 1;
1011 case MIIM_LXT971_SR2_100HDX:
1013 priv->duplexity = 0;
1016 priv->duplexity = 1;
1021 priv->duplexity = 0;
1027 static struct phy_info phy_info_lxt971 = {
1031 (struct phy_cmd []) { /* config */
1032 { MIIM_CR, MIIM_CR_INIT, mii_cr_init }, /* autonegotiate */
1035 (struct phy_cmd []) { /* startup - enable interrupts */
1036 /* { 0x12, 0x00f2, NULL }, */
1037 { MIIM_STATUS, miim_read, NULL },
1038 { MIIM_STATUS, miim_read, &mii_parse_sr },
1039 { MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2 },
1042 (struct phy_cmd []) { /* shutdown - disable interrupts */
1047 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1049 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1051 switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1053 case MIIM_DP83865_SPD_1000:
1057 case MIIM_DP83865_SPD_100:
1067 if (mii_reg & MIIM_DP83865_DPX_FULL)
1068 priv->duplexity = 1;
1070 priv->duplexity = 0;
1075 struct phy_info phy_info_dp83865 = {
1079 (struct phy_cmd[]) { /* config */
1080 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1083 (struct phy_cmd[]) { /* startup */
1084 /* Status is read once to clear old link state */
1085 {MIIM_STATUS, miim_read, NULL},
1086 /* Auto-negotiate */
1087 {MIIM_STATUS, miim_read, &mii_parse_sr},
1088 /* Read the link and auto-neg status */
1089 {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr},
1092 (struct phy_cmd[]) { /* shutdown */
1097 struct phy_info *phy_info[] = {
1102 &phy_info_M88E1011S,
1103 &phy_info_M88E1111S,
1113 /* Grab the identifier of the device's PHY, and search through
1114 * all of the known PHYs to see if one matches. If so, return
1115 * it, if not, return NULL */
1116 struct phy_info * get_phy_info(struct eth_device *dev)
1118 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1119 uint phy_reg, phy_ID;
1121 struct phy_info *theInfo = NULL;
1123 /* Grab the bits from PHYIR1, and put them in the upper half */
1124 phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1125 phy_ID = (phy_reg & 0xffff) << 16;
1127 /* Grab the bits from PHYIR2, and put them in the lower half */
1128 phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1129 phy_ID |= (phy_reg & 0xffff);
1131 /* loop through all the known PHY types, and find one that */
1132 /* matches the ID we read from the PHY. */
1133 for(i=0; phy_info[i]; i++) {
1134 if(phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
1135 theInfo = phy_info[i];
1140 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
1143 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1150 /* Execute the given series of commands on the given device's
1151 * PHY, running functions as necessary*/
1152 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1156 volatile tsec_t *phyregs = priv->phyregs;
1158 phyregs->miimcfg = MIIMCFG_RESET;
1160 phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1162 while(phyregs->miimind & MIIMIND_BUSY);
1164 for(i=0;cmd->mii_reg != miim_end;i++) {
1165 if(cmd->mii_data == miim_read) {
1166 result = read_phy_reg(priv, cmd->mii_reg);
1168 if(cmd->funct != NULL)
1169 (*(cmd->funct))(result, priv);
1172 if(cmd->funct != NULL)
1173 result = (*(cmd->funct))(cmd->mii_reg, priv);
1175 result = cmd->mii_data;
1177 write_phy_reg(priv, cmd->mii_reg, result);
1185 /* Relocate the function pointers in the phy cmd lists */
1186 static void relocate_cmds(void)
1188 struct phy_cmd **cmdlistptr;
1189 struct phy_cmd *cmd;
1192 for(i=0; phy_info[i]; i++) {
1193 /* First thing's first: relocate the pointers to the
1194 * PHY command structures (the structs were done) */
1195 phy_info[i] = (struct phy_info *) ((uint)phy_info[i]
1197 phy_info[i]->name += gd->reloc_off;
1198 phy_info[i]->config =
1199 (struct phy_cmd *)((uint)phy_info[i]->config
1201 phy_info[i]->startup =
1202 (struct phy_cmd *)((uint)phy_info[i]->startup
1204 phy_info[i]->shutdown =
1205 (struct phy_cmd *)((uint)phy_info[i]->shutdown
1208 cmdlistptr = &phy_info[i]->config;
1210 for(;cmdlistptr <= &phy_info[i]->shutdown;cmdlistptr++) {
1212 for(cmd=*cmdlistptr;cmd->mii_reg != miim_end;cmd++) {
1213 /* Only relocate non-NULL pointers */
1215 cmd->funct += gd->reloc_off;
1227 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
1228 && !defined(BITBANGMII)
1230 struct tsec_private * get_priv_for_phy(unsigned char phyaddr)
1234 for(i=0;i<MAXCONTROLLERS;i++) {
1235 if(privlist[i]->phyaddr == phyaddr)
1243 * Read a MII PHY register.
1248 static int tsec_miiphy_read(char *devname, unsigned char addr,
1249 unsigned char reg, unsigned short *value)
1252 struct tsec_private *priv = get_priv_for_phy(addr);
1255 printf("Can't read PHY at address %d\n", addr);
1259 ret = (unsigned short)read_phy_reg(priv, reg);
1266 * Write a MII PHY register.
1271 static int tsec_miiphy_write(char *devname, unsigned char addr,
1272 unsigned char reg, unsigned short value)
1274 struct tsec_private *priv = get_priv_for_phy(addr);
1277 printf("Can't write PHY at address %d\n", addr);
1281 write_phy_reg(priv, reg, value);
1286 #endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1287 && !defined(BITBANGMII) */
1289 #endif /* CONFIG_TSEC_ENET */