1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
4 * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
6 * Copyright (C) 2009 for Samsung Electronics
8 * BSP Support for Samsung's UDC driver
10 * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
12 * State machine bugfixes:
13 * Marek Szyprowski <m.szyprowski@samsung.com>
16 * Marek Szyprowski <m.szyprowski@samsung.com>
17 * Lukasz Majewski <l.majewski@samsumg.com>
20 static u8 clear_feature_num;
21 int clear_feature_flag;
23 /* Bulk-Only Mass Storage Reset (class-specific request) */
24 #define GET_MAX_LUN_REQUEST 0xFE
25 #define BOT_RESET_REQUEST 0xFF
27 static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev)
31 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
32 writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz);
34 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
35 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
36 ®->in_endp[EP0_CON].diepctl);
38 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
39 __func__, readl(®->in_endp[EP0_CON].diepctl));
40 dev->ep0state = WAIT_FOR_IN_COMPLETE;
43 static void dwc2_udc_pre_setup(void)
47 debug_cond(DEBUG_IN_EP,
48 "%s : Prepare Setup packets.\n", __func__);
50 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
51 ®->out_endp[EP0_CON].doeptsiz);
52 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
54 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
55 writel(ep_ctrl|DEPCTL_EPENA, ®->out_endp[EP0_CON].doepctl);
57 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
58 __func__, readl(®->in_endp[EP0_CON].diepctl));
59 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
60 __func__, readl(®->out_endp[EP0_CON].doepctl));
64 static inline void dwc2_ep0_complete_out(void)
68 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
69 __func__, readl(®->in_endp[EP0_CON].diepctl));
70 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
71 __func__, readl(®->out_endp[EP0_CON].doepctl));
73 debug_cond(DEBUG_IN_EP,
74 "%s : Prepare Complete Out packet.\n", __func__);
76 writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
77 ®->out_endp[EP0_CON].doeptsiz);
78 writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma);
80 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
81 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
82 ®->out_endp[EP0_CON].doepctl);
84 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
85 __func__, readl(®->in_endp[EP0_CON].diepctl));
86 debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
87 __func__, readl(®->out_endp[EP0_CON].doepctl));
92 static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req)
96 u32 ep_num = ep_index(ep);
98 buf = req->req.buf + req->req.actual;
99 length = min_t(u32, req->req.length - req->req.actual,
100 ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket);
105 if (ep_num == EP0_CON || length == 0)
108 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
110 ctrl = readl(®->out_endp[ep_num].doepctl);
112 invalidate_dcache_range((unsigned long) ep->dma_buf,
113 (unsigned long) ep->dma_buf +
114 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
116 writel((unsigned long) ep->dma_buf, ®->out_endp[ep_num].doepdma);
117 writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
118 ®->out_endp[ep_num].doeptsiz);
119 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl);
121 debug_cond(DEBUG_OUT_EP != 0,
122 "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
123 "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
124 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
126 readl(®->out_endp[ep_num].doepdma),
127 readl(®->out_endp[ep_num].doeptsiz),
128 readl(®->out_endp[ep_num].doepctl),
129 buf, pktcnt, length);
134 static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req)
138 u32 ep_num = ep_index(ep);
140 buf = req->req.buf + req->req.actual;
141 length = req->req.length - req->req.actual;
143 if (ep_num == EP0_CON)
144 length = min(length, (u32)ep_maxpacket(ep));
149 flush_dcache_range((unsigned long) ep->dma_buf,
150 (unsigned long) ep->dma_buf +
151 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
156 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
158 /* Flush the endpoint's Tx FIFO */
159 writel(TX_FIFO_NUMBER(ep->fifo_num), ®->grstctl);
160 writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, ®->grstctl);
161 while (readl(®->grstctl) & TX_FIFO_FLUSH)
164 writel((unsigned long) ep->dma_buf, ®->in_endp[ep_num].diepdma);
165 writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
166 ®->in_endp[ep_num].dieptsiz);
168 ctrl = readl(®->in_endp[ep_num].diepctl);
170 /* Write the FIFO number to be used for this endpoint */
171 ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
172 ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
174 /* Clear reserved (Next EP) bits */
175 ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
177 writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->in_endp[ep_num].diepctl);
179 debug_cond(DEBUG_IN_EP,
180 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
181 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
182 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
184 readl(®->in_endp[ep_num].diepdma),
185 readl(®->in_endp[ep_num].dieptsiz),
186 readl(®->in_endp[ep_num].diepctl),
187 buf, pktcnt, length);
192 static void complete_rx(struct dwc2_udc *dev, u8 ep_num)
194 struct dwc2_ep *ep = &dev->ep[ep_num];
195 struct dwc2_request *req = NULL;
196 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
198 if (list_empty(&ep->queue)) {
199 debug_cond(DEBUG_OUT_EP != 0,
200 "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
206 req = list_entry(ep->queue.next, struct dwc2_request, queue);
207 ep_tsr = readl(®->out_endp[ep_num].doeptsiz);
209 if (ep_num == EP0_CON)
210 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
212 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
214 xfer_size = ep->len - xfer_size;
219 * Please be careful with proper buffer allocation for USB request,
220 * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only
221 * with starting address, but also its size shall be a cache line
224 * This will prevent from corruption of data allocated immediatelly
225 * before or after the buffer.
227 * For armv7, the cache_v7.c provides proper code to emit "ERROR"
228 * message to warn users.
230 invalidate_dcache_range((unsigned long) ep->dma_buf,
231 (unsigned long) ep->dma_buf +
232 ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE));
234 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
235 is_short = !!(xfer_size % ep->ep.maxpacket);
237 debug_cond(DEBUG_OUT_EP != 0,
238 "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
239 "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
240 __func__, ep_num, req->req.actual, req->req.length,
241 is_short, ep_tsr, req->req.length - req->req.actual);
243 if (is_short || req->req.actual == req->req.length) {
244 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
245 debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n");
246 dwc2_udc_ep0_zlp(dev);
247 /* packet will be completed in complete_tx() */
248 dev->ep0state = WAIT_FOR_IN_COMPLETE;
252 if (!list_empty(&ep->queue)) {
253 req = list_entry(ep->queue.next,
254 struct dwc2_request, queue);
255 debug_cond(DEBUG_OUT_EP != 0,
256 "%s: Next Rx request start...\n",
265 static void complete_tx(struct dwc2_udc *dev, u8 ep_num)
267 struct dwc2_ep *ep = &dev->ep[ep_num];
268 struct dwc2_request *req;
269 u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
272 if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
273 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
274 dwc2_ep0_complete_out();
278 if (list_empty(&ep->queue)) {
279 debug_cond(DEBUG_IN_EP,
280 "%s: TX DMA done : NULL REQ on IN EP-%d\n",
286 req = list_entry(ep->queue.next, struct dwc2_request, queue);
288 ep_tsr = readl(®->in_endp[ep_num].dieptsiz);
291 is_short = (xfer_size < ep->ep.maxpacket);
292 req->req.actual += min(xfer_size, req->req.length - req->req.actual);
294 debug_cond(DEBUG_IN_EP,
295 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
296 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
297 __func__, ep_num, req->req.actual, req->req.length,
298 is_short, ep_tsr, req->req.length - req->req.actual);
301 if (dev->ep0state == DATA_STATE_XMIT) {
302 debug_cond(DEBUG_IN_EP,
303 "%s: ep_num = %d, ep0stat =="
306 last = write_fifo_ep0(ep, req);
308 dev->ep0state = WAIT_FOR_COMPLETE;
309 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
310 debug_cond(DEBUG_IN_EP,
311 "%s: ep_num = %d, completing request\n",
314 dev->ep0state = WAIT_FOR_SETUP;
315 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
316 debug_cond(DEBUG_IN_EP,
317 "%s: ep_num = %d, completing request\n",
320 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
321 dwc2_ep0_complete_out();
323 debug_cond(DEBUG_IN_EP,
324 "%s: ep_num = %d, invalid ep state\n",
330 if (req->req.actual == req->req.length)
333 if (!list_empty(&ep->queue)) {
334 req = list_entry(ep->queue.next, struct dwc2_request, queue);
335 debug_cond(DEBUG_IN_EP,
336 "%s: Next Tx request start...\n", __func__);
341 static inline void dwc2_udc_check_tx_queue(struct dwc2_udc *dev, u8 ep_num)
343 struct dwc2_ep *ep = &dev->ep[ep_num];
344 struct dwc2_request *req;
346 debug_cond(DEBUG_IN_EP,
347 "%s: Check queue, ep_num = %d\n", __func__, ep_num);
349 if (!list_empty(&ep->queue)) {
350 req = list_entry(ep->queue.next, struct dwc2_request, queue);
351 debug_cond(DEBUG_IN_EP,
352 "%s: Next Tx request(0x%p) start...\n",
360 debug_cond(DEBUG_IN_EP,
361 "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
368 static void process_ep_in_intr(struct dwc2_udc *dev)
370 u32 ep_intr, ep_intr_status;
373 ep_intr = readl(®->daint);
374 debug_cond(DEBUG_IN_EP,
375 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
377 ep_intr &= DAINT_MASK;
380 if (ep_intr & DAINT_IN_EP_INT(1)) {
381 ep_intr_status = readl(®->in_endp[ep_num].diepint);
382 debug_cond(DEBUG_IN_EP,
383 "\tEP%d-IN : DIEPINT = 0x%x\n",
384 ep_num, ep_intr_status);
386 /* Interrupt Clear */
387 writel(ep_intr_status, ®->in_endp[ep_num].diepint);
389 if (ep_intr_status & TRANSFER_DONE) {
390 complete_tx(dev, ep_num);
394 WAIT_FOR_IN_COMPLETE)
395 dev->ep0state = WAIT_FOR_SETUP;
397 if (dev->ep0state == WAIT_FOR_SETUP)
398 dwc2_udc_pre_setup();
400 /* continue transfer after
401 set_clear_halt for DMA mode */
402 if (clear_feature_flag == 1) {
403 dwc2_udc_check_tx_queue(dev,
405 clear_feature_flag = 0;
415 static void process_ep_out_intr(struct dwc2_udc *dev)
417 u32 ep_intr, ep_intr_status;
420 ep_intr = readl(®->daint);
421 debug_cond(DEBUG_OUT_EP != 0,
422 "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
425 ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
429 ep_intr_status = readl(®->out_endp[ep_num].doepint);
430 debug_cond(DEBUG_OUT_EP != 0,
431 "\tEP%d-OUT : DOEPINT = 0x%x\n",
432 ep_num, ep_intr_status);
434 /* Interrupt Clear */
435 writel(ep_intr_status, ®->out_endp[ep_num].doepint);
438 if (ep_intr_status & TRANSFER_DONE) {
440 WAIT_FOR_OUT_COMPLETE)
441 complete_rx(dev, ep_num);
443 dev->ep0state = WAIT_FOR_SETUP;
444 dwc2_udc_pre_setup();
449 CTRL_OUT_EP_SETUP_PHASE_DONE) {
450 debug_cond(DEBUG_OUT_EP != 0,
451 "SETUP packet arrived\n");
452 dwc2_handle_ep0(dev);
455 if (ep_intr_status & TRANSFER_DONE)
456 complete_rx(dev, ep_num);
465 * usb client interrupt handler.
467 static int dwc2_udc_irq(int irq, void *_dev)
469 struct dwc2_udc *dev = _dev;
471 u32 usb_status, gintmsk;
472 unsigned long flags = 0;
474 spin_lock_irqsave(&dev->lock, flags);
476 intr_status = readl(®->gintsts);
477 gintmsk = readl(®->gintmsk);
479 debug_cond(DEBUG_ISR,
480 "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
481 "DAINT : 0x%x, DAINTMSK : 0x%x\n",
482 __func__, intr_status, state_names[dev->ep0state], gintmsk,
483 readl(®->daint), readl(®->daintmsk));
486 spin_unlock_irqrestore(&dev->lock, flags);
490 if (intr_status & INT_ENUMDONE) {
491 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
493 writel(INT_ENUMDONE, ®->gintsts);
494 usb_status = (readl(®->dsts) & 0x6);
496 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
497 debug_cond(DEBUG_ISR,
498 "\t\tFull Speed Detection\n");
499 set_max_pktsize(dev, USB_SPEED_FULL);
502 debug_cond(DEBUG_ISR,
503 "\t\tHigh Speed Detection : 0x%x\n",
505 set_max_pktsize(dev, USB_SPEED_HIGH);
509 if (intr_status & INT_EARLY_SUSPEND) {
510 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
511 writel(INT_EARLY_SUSPEND, ®->gintsts);
514 if (intr_status & INT_SUSPEND) {
515 usb_status = readl(®->dsts);
516 debug_cond(DEBUG_ISR,
517 "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
518 writel(INT_SUSPEND, ®->gintsts);
520 if (dev->gadget.speed != USB_SPEED_UNKNOWN
522 if (dev->driver->suspend)
523 dev->driver->suspend(&dev->gadget);
525 /* HACK to let gadget detect disconnected state */
526 if (dev->driver->disconnect) {
527 spin_unlock_irqrestore(&dev->lock, flags);
528 dev->driver->disconnect(&dev->gadget);
529 spin_lock_irqsave(&dev->lock, flags);
534 if (intr_status & INT_RESUME) {
535 debug_cond(DEBUG_ISR, "\tResume interrupt\n");
536 writel(INT_RESUME, ®->gintsts);
538 if (dev->gadget.speed != USB_SPEED_UNKNOWN
540 && dev->driver->resume) {
542 dev->driver->resume(&dev->gadget);
546 if (intr_status & INT_RESET) {
547 usb_status = readl(®->gotgctl);
548 debug_cond(DEBUG_ISR,
549 "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
550 writel(INT_RESET, ®->gintsts);
552 if ((usb_status & 0xc0000) == (0x3 << 18)) {
553 if (reset_available) {
554 debug_cond(DEBUG_ISR,
555 "\t\tOTG core got reset (%d)!!\n",
558 dev->ep0state = WAIT_FOR_SETUP;
560 dwc2_udc_pre_setup();
566 debug_cond(DEBUG_ISR,
567 "\t\tRESET handling skipped\n");
571 if (intr_status & INT_IN_EP)
572 process_ep_in_intr(dev);
574 if (intr_status & INT_OUT_EP)
575 process_ep_out_intr(dev);
577 spin_unlock_irqrestore(&dev->lock, flags);
582 /** Queue one request
583 * Kickstart transfer if needed
585 static int dwc2_queue(struct usb_ep *_ep, struct usb_request *_req,
588 struct dwc2_request *req;
590 struct dwc2_udc *dev;
591 unsigned long flags = 0;
594 req = container_of(_req, struct dwc2_request, req);
595 if (unlikely(!_req || !_req->complete || !_req->buf
596 || !list_empty(&req->queue))) {
598 debug("%s: bad params\n", __func__);
602 ep = container_of(_ep, struct dwc2_ep, ep);
604 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
606 debug("%s: bad ep: %s, %d, %p\n", __func__,
607 ep->ep.name, !ep->desc, _ep);
611 ep_num = ep_index(ep);
613 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
615 debug("%s: bogus device state %p\n", __func__, dev->driver);
619 spin_lock_irqsave(&dev->lock, flags);
621 _req->status = -EINPROGRESS;
624 /* kickstart this i/o queue? */
625 debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
626 "Q empty = %d, stopped = %d\n",
627 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
628 _req, _req->length, _req->buf,
629 list_empty(&ep->queue), ep->stopped);
633 int i, len = _req->length;
638 for (i = 0; i < len; i++) {
639 printf("%02x", ((u8 *)_req->buf)[i]);
647 if (list_empty(&ep->queue) && !ep->stopped) {
651 list_add_tail(&req->queue, &ep->queue);
652 dwc2_ep0_kick(dev, ep);
655 } else if (ep_is_in(ep)) {
656 gintsts = readl(®->gintsts);
657 debug_cond(DEBUG_IN_EP,
658 "%s: ep_is_in, DWC2_UDC_OTG_GINTSTS=0x%x\n",
663 gintsts = readl(®->gintsts);
664 debug_cond(DEBUG_OUT_EP != 0,
665 "%s:ep_is_out, DWC2_UDC_OTG_GINTSTS=0x%x\n",
672 /* pio or dma irq handler advances the queue. */
673 if (likely(req != 0))
674 list_add_tail(&req->queue, &ep->queue);
676 spin_unlock_irqrestore(&dev->lock, flags);
681 /****************************************************************/
682 /* End Point 0 related functions */
683 /****************************************************************/
685 /* return: 0 = still running, 1 = completed, negative = errno */
686 static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req)
692 max = ep_maxpacket(ep);
694 debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
696 count = setdma_tx(ep, req);
698 /* last packet is usually short (or a zlp) */
699 if (likely(count != max))
702 if (likely(req->req.length != req->req.actual + count)
709 debug_cond(DEBUG_EP0 != 0,
710 "%s: wrote %s %d bytes%s %d left %p\n", __func__,
713 req->req.length - req->req.actual - count, req);
715 /* requests complete when all IN data is in the FIFO */
717 ep->dev->ep0state = WAIT_FOR_SETUP;
724 static int dwc2_fifo_read(struct dwc2_ep *ep, u32 *cp, int max)
726 invalidate_dcache_range((unsigned long)cp, (unsigned long)cp +
727 ROUND(max, CONFIG_SYS_CACHELINE_SIZE));
729 debug_cond(DEBUG_EP0 != 0,
730 "%s: bytes=%d, ep_index=%d 0x%p\n", __func__,
731 max, ep_index(ep), cp);
737 * udc_set_address - set the USB address for this device
740 * Called from control endpoint function
741 * after it decodes a set address setup packet.
743 static void udc_set_address(struct dwc2_udc *dev, unsigned char address)
745 u32 ctrl = readl(®->dcfg);
746 writel(DEVICE_ADDRESS(address) | ctrl, ®->dcfg);
748 dwc2_udc_ep0_zlp(dev);
750 debug_cond(DEBUG_EP0 != 0,
751 "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
752 __func__, address, readl(®->dcfg));
754 dev->usb_address = address;
757 static inline void dwc2_udc_ep0_set_stall(struct dwc2_ep *ep)
759 struct dwc2_udc *dev;
763 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
765 /* set the disable and stall bits */
766 if (ep_ctrl & DEPCTL_EPENA)
767 ep_ctrl |= DEPCTL_EPDIS;
769 ep_ctrl |= DEPCTL_STALL;
771 writel(ep_ctrl, ®->in_endp[EP0_CON].diepctl);
773 debug_cond(DEBUG_EP0 != 0,
774 "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
775 __func__, ep_index(ep), ®->in_endp[EP0_CON].diepctl);
777 * The application can only set this bit, and the core clears it,
778 * when a SETUP token is received for this endpoint
780 dev->ep0state = WAIT_FOR_SETUP;
782 dwc2_udc_pre_setup();
785 static void dwc2_ep0_read(struct dwc2_udc *dev)
787 struct dwc2_request *req;
788 struct dwc2_ep *ep = &dev->ep[0];
790 if (!list_empty(&ep->queue)) {
791 req = list_entry(ep->queue.next, struct dwc2_request, queue);
794 debug("%s: ---> BUG\n", __func__);
799 debug_cond(DEBUG_EP0 != 0,
800 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
801 __func__, req, req->req.length, req->req.actual);
803 if (req->req.length == 0) {
804 /* zlp for Set_configuration, Set_interface,
805 * or Bulk-Only mass storge reset */
808 dwc2_udc_ep0_zlp(dev);
810 debug_cond(DEBUG_EP0 != 0,
811 "%s: req.length = 0, bRequest = %d\n",
812 __func__, usb_ctrl->bRequest);
822 static int dwc2_ep0_write(struct dwc2_udc *dev)
824 struct dwc2_request *req;
825 struct dwc2_ep *ep = &dev->ep[0];
826 int ret, need_zlp = 0;
828 if (list_empty(&ep->queue))
831 req = list_entry(ep->queue.next, struct dwc2_request, queue);
834 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
838 debug_cond(DEBUG_EP0 != 0,
839 "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
840 __func__, req, req->req.length, req->req.actual);
842 if (req->req.length - req->req.actual == ep0_fifo_size) {
843 /* Next write will end with the packet size, */
844 /* so we need Zero-length-packet */
848 ret = write_fifo_ep0(ep, req);
850 if ((ret == 1) && !need_zlp) {
852 dev->ep0state = WAIT_FOR_COMPLETE;
853 debug_cond(DEBUG_EP0 != 0,
854 "%s: finished, waiting for status\n", __func__);
857 dev->ep0state = DATA_STATE_XMIT;
858 debug_cond(DEBUG_EP0 != 0,
859 "%s: not finished\n", __func__);
865 static int dwc2_udc_get_status(struct dwc2_udc *dev,
866 struct usb_ctrlrequest *crq)
868 u8 ep_num = crq->wIndex & 0x7F;
872 debug_cond(DEBUG_SETUP != 0,
873 "%s: *** USB_REQ_GET_STATUS\n", __func__);
874 printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
875 switch (crq->bRequestType & USB_RECIP_MASK) {
876 case USB_RECIP_INTERFACE:
878 debug_cond(DEBUG_SETUP != 0,
879 "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
883 case USB_RECIP_DEVICE:
884 g_status = 0x1; /* Self powered */
885 debug_cond(DEBUG_SETUP != 0,
886 "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
890 case USB_RECIP_ENDPOINT:
891 if (crq->wLength > 2) {
892 debug_cond(DEBUG_SETUP != 0,
893 "\tGET_STATUS:Not support EP or wLength\n");
897 g_status = dev->ep[ep_num].stopped;
898 debug_cond(DEBUG_SETUP != 0,
899 "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
908 memcpy(usb_ctrl, &g_status, sizeof(g_status));
910 flush_dcache_range((unsigned long) usb_ctrl,
911 (unsigned long) usb_ctrl +
912 ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE));
914 writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
915 writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
916 ®->in_endp[EP0_CON].dieptsiz);
918 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
919 writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
920 ®->in_endp[EP0_CON].diepctl);
921 dev->ep0state = WAIT_FOR_NULL_COMPLETE;
926 static void dwc2_udc_set_nak(struct dwc2_ep *ep)
931 ep_num = ep_index(ep);
932 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
935 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
936 ep_ctrl |= DEPCTL_SNAK;
937 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
938 debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
939 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
941 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
942 ep_ctrl |= DEPCTL_SNAK;
943 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
944 debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
945 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
952 static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep)
957 ep_num = ep_index(ep);
958 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
961 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
963 /* set the disable and stall bits */
964 if (ep_ctrl & DEPCTL_EPENA)
965 ep_ctrl |= DEPCTL_EPDIS;
967 ep_ctrl |= DEPCTL_STALL;
969 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
970 debug("%s: set stall, DIEPCTL%d = 0x%x\n",
971 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
974 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
976 /* set the stall bit */
977 ep_ctrl |= DEPCTL_STALL;
979 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
980 debug("%s: set stall, DOEPCTL%d = 0x%x\n",
981 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
987 static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep)
992 ep_num = ep_index(ep);
993 debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
996 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
998 /* clear stall bit */
999 ep_ctrl &= ~DEPCTL_STALL;
1002 * USB Spec 9.4.5: For endpoints using data toggle, regardless
1003 * of whether an endpoint has the Halt feature set, a
1004 * ClearFeature(ENDPOINT_HALT) request always results in the
1005 * data toggle being reinitialized to DATA0.
1007 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1008 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1009 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1012 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1013 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1014 __func__, ep_num, readl(®->in_endp[ep_num].diepctl));
1017 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1019 /* clear stall bit */
1020 ep_ctrl &= ~DEPCTL_STALL;
1022 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1023 || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1024 ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1027 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1028 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1029 __func__, ep_num, readl(®->out_endp[ep_num].doepctl));
1035 static int dwc2_udc_set_halt(struct usb_ep *_ep, int value)
1038 struct dwc2_udc *dev;
1039 unsigned long flags = 0;
1042 ep = container_of(_ep, struct dwc2_ep, ep);
1043 ep_num = ep_index(ep);
1045 if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1046 ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1047 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1051 /* Attempt to halt IN ep will fail if any transfer requests
1052 * are still queue */
1053 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1054 debug("%s: %s queue not empty, req = %p\n",
1055 __func__, ep->ep.name,
1056 list_entry(ep->queue.next, struct dwc2_request, queue));
1062 debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1064 spin_lock_irqsave(&dev->lock, flags);
1068 dwc2_udc_ep_clear_stall(ep);
1071 dev->ep0state = WAIT_FOR_SETUP;
1074 dwc2_udc_ep_set_stall(ep);
1077 spin_unlock_irqrestore(&dev->lock, flags);
1082 static void dwc2_udc_ep_activate(struct dwc2_ep *ep)
1085 u32 ep_ctrl = 0, daintmsk = 0;
1087 ep_num = ep_index(ep);
1089 /* Read DEPCTLn register */
1091 ep_ctrl = readl(®->in_endp[ep_num].diepctl);
1092 daintmsk = 1 << ep_num;
1094 ep_ctrl = readl(®->out_endp[ep_num].doepctl);
1095 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1098 debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1099 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1101 /* If the EP is already active don't change the EP Control
1103 if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1104 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1105 (ep->bmAttributes << DEPCTL_TYPE_BIT);
1106 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1107 (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1108 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1111 writel(ep_ctrl, ®->in_endp[ep_num].diepctl);
1112 debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1113 __func__, ep_num, ep_num,
1114 readl(®->in_endp[ep_num].diepctl));
1116 writel(ep_ctrl, ®->out_endp[ep_num].doepctl);
1117 debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1118 __func__, ep_num, ep_num,
1119 readl(®->out_endp[ep_num].doepctl));
1123 /* Unmask EP Interrtupt */
1124 writel(readl(®->daintmsk)|daintmsk, ®->daintmsk);
1125 debug("%s: DAINTMSK = 0x%x\n", __func__, readl(®->daintmsk));
1129 static int dwc2_udc_clear_feature(struct usb_ep *_ep)
1131 struct dwc2_udc *dev;
1135 ep = container_of(_ep, struct dwc2_ep, ep);
1136 ep_num = ep_index(ep);
1139 debug_cond(DEBUG_SETUP != 0,
1140 "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1141 __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1143 if (usb_ctrl->wLength != 0) {
1144 debug_cond(DEBUG_SETUP != 0,
1145 "\tCLEAR_FEATURE: wLength is not zero.....\n");
1149 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1150 case USB_RECIP_DEVICE:
1151 switch (usb_ctrl->wValue) {
1152 case USB_DEVICE_REMOTE_WAKEUP:
1153 debug_cond(DEBUG_SETUP != 0,
1154 "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1157 case USB_DEVICE_TEST_MODE:
1158 debug_cond(DEBUG_SETUP != 0,
1159 "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1160 /** @todo Add CLEAR_FEATURE for TEST modes. */
1164 dwc2_udc_ep0_zlp(dev);
1167 case USB_RECIP_ENDPOINT:
1168 debug_cond(DEBUG_SETUP != 0,
1169 "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1172 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1174 dwc2_udc_ep0_set_stall(ep);
1178 dwc2_udc_ep0_zlp(dev);
1180 dwc2_udc_ep_clear_stall(ep);
1181 dwc2_udc_ep_activate(ep);
1184 clear_feature_num = ep_num;
1185 clear_feature_flag = 1;
1193 static int dwc2_udc_set_feature(struct usb_ep *_ep)
1195 struct dwc2_udc *dev;
1199 ep = container_of(_ep, struct dwc2_ep, ep);
1200 ep_num = ep_index(ep);
1203 debug_cond(DEBUG_SETUP != 0,
1204 "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1207 if (usb_ctrl->wLength != 0) {
1208 debug_cond(DEBUG_SETUP != 0,
1209 "\tSET_FEATURE: wLength is not zero.....\n");
1213 switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1214 case USB_RECIP_DEVICE:
1215 switch (usb_ctrl->wValue) {
1216 case USB_DEVICE_REMOTE_WAKEUP:
1217 debug_cond(DEBUG_SETUP != 0,
1218 "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1220 case USB_DEVICE_B_HNP_ENABLE:
1221 debug_cond(DEBUG_SETUP != 0,
1222 "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1225 case USB_DEVICE_A_HNP_SUPPORT:
1226 /* RH port supports HNP */
1227 debug_cond(DEBUG_SETUP != 0,
1228 "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1231 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1232 /* other RH port does */
1233 debug_cond(DEBUG_SETUP != 0,
1234 "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1238 dwc2_udc_ep0_zlp(dev);
1241 case USB_RECIP_INTERFACE:
1242 debug_cond(DEBUG_SETUP != 0,
1243 "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1246 case USB_RECIP_ENDPOINT:
1247 debug_cond(DEBUG_SETUP != 0,
1248 "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1249 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1251 dwc2_udc_ep0_set_stall(ep);
1255 dwc2_udc_ep_set_stall(ep);
1258 dwc2_udc_ep0_zlp(dev);
1266 * WAIT_FOR_SETUP (OUT_PKT_RDY)
1268 static void dwc2_ep0_setup(struct dwc2_udc *dev)
1270 struct dwc2_ep *ep = &dev->ep[0];
1274 /* Nuke all previous transfers */
1277 /* read control req from fifo (8 bytes) */
1278 dwc2_fifo_read(ep, (u32 *)usb_ctrl, 8);
1280 debug_cond(DEBUG_SETUP != 0,
1281 "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1282 "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1283 __func__, usb_ctrl->bRequestType,
1284 (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1286 usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1290 int i, len = sizeof(*usb_ctrl);
1291 char *p = (char *)usb_ctrl;
1294 for (i = 0; i < len; i++) {
1295 printf("%02x", ((u8 *)p)[i]);
1303 if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1304 usb_ctrl->wLength != 1) {
1305 debug_cond(DEBUG_SETUP != 0,
1306 "\t%s:GET_MAX_LUN_REQUEST:invalid",
1308 debug_cond(DEBUG_SETUP != 0,
1309 "wLength = %d, setup returned\n",
1312 dwc2_udc_ep0_set_stall(ep);
1313 dev->ep0state = WAIT_FOR_SETUP;
1316 } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1317 usb_ctrl->wLength != 0) {
1318 /* Bulk-Only *mass storge reset of class-specific request */
1319 debug_cond(DEBUG_SETUP != 0,
1320 "%s:BOT Rest:invalid wLength =%d, setup returned\n",
1321 __func__, usb_ctrl->wLength);
1323 dwc2_udc_ep0_set_stall(ep);
1324 dev->ep0state = WAIT_FOR_SETUP;
1329 /* Set direction of EP0 */
1330 if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1331 ep->bEndpointAddress |= USB_DIR_IN;
1333 ep->bEndpointAddress &= ~USB_DIR_IN;
1335 /* cope with automagic for some standard requests. */
1336 dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1337 == USB_TYPE_STANDARD;
1339 dev->req_pending = 1;
1341 /* Handle some SETUP packets ourselves */
1343 switch (usb_ctrl->bRequest) {
1344 case USB_REQ_SET_ADDRESS:
1345 debug_cond(DEBUG_SETUP != 0,
1346 "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1347 __func__, usb_ctrl->wValue);
1348 if (usb_ctrl->bRequestType
1349 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1352 udc_set_address(dev, usb_ctrl->wValue);
1355 case USB_REQ_SET_CONFIGURATION:
1356 debug_cond(DEBUG_SETUP != 0,
1357 "=====================================\n");
1358 debug_cond(DEBUG_SETUP != 0,
1359 "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1360 __func__, usb_ctrl->wValue);
1362 if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
1363 reset_available = 1;
1367 case USB_REQ_GET_DESCRIPTOR:
1368 debug_cond(DEBUG_SETUP != 0,
1369 "%s: *** USB_REQ_GET_DESCRIPTOR\n",
1373 case USB_REQ_SET_INTERFACE:
1374 debug_cond(DEBUG_SETUP != 0,
1375 "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1376 __func__, usb_ctrl->wValue);
1378 if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
1379 reset_available = 1;
1383 case USB_REQ_GET_CONFIGURATION:
1384 debug_cond(DEBUG_SETUP != 0,
1385 "%s: *** USB_REQ_GET_CONFIGURATION\n",
1389 case USB_REQ_GET_STATUS:
1390 if (!dwc2_udc_get_status(dev, usb_ctrl))
1395 case USB_REQ_CLEAR_FEATURE:
1396 ep_num = usb_ctrl->wIndex & 0x7f;
1398 if (!dwc2_udc_clear_feature(&dev->ep[ep_num].ep))
1403 case USB_REQ_SET_FEATURE:
1404 ep_num = usb_ctrl->wIndex & 0x7f;
1406 if (!dwc2_udc_set_feature(&dev->ep[ep_num].ep))
1412 debug_cond(DEBUG_SETUP != 0,
1413 "%s: *** Default of usb_ctrl->bRequest=0x%x"
1414 "happened.\n", __func__, usb_ctrl->bRequest);
1420 if (likely(dev->driver)) {
1421 /* device-2-host (IN) or no data setup command,
1422 * process immediately */
1423 debug_cond(DEBUG_SETUP != 0,
1424 "%s:usb_ctrlreq will be passed to fsg_setup()\n",
1427 spin_unlock(&dev->lock);
1428 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1429 spin_lock(&dev->lock);
1432 /* setup processing failed, force stall */
1433 dwc2_udc_ep0_set_stall(ep);
1434 dev->ep0state = WAIT_FOR_SETUP;
1436 debug_cond(DEBUG_SETUP != 0,
1437 "\tdev->driver->setup failed (%d),"
1439 i, usb_ctrl->bRequest);
1442 } else if (dev->req_pending) {
1443 dev->req_pending = 0;
1444 debug_cond(DEBUG_SETUP != 0,
1445 "\tdev->req_pending...\n");
1448 debug_cond(DEBUG_SETUP != 0,
1449 "\tep0state = %s\n", state_names[dev->ep0state]);
1455 * handle ep0 interrupt
1457 static void dwc2_handle_ep0(struct dwc2_udc *dev)
1459 if (dev->ep0state == WAIT_FOR_SETUP) {
1460 debug_cond(DEBUG_OUT_EP != 0,
1461 "%s: WAIT_FOR_SETUP\n", __func__);
1462 dwc2_ep0_setup(dev);
1465 debug_cond(DEBUG_OUT_EP != 0,
1466 "%s: strange state!!(state = %s)\n",
1467 __func__, state_names[dev->ep0state]);
1471 static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep)
1473 debug_cond(DEBUG_EP0 != 0,
1474 "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1476 dev->ep0state = DATA_STATE_XMIT;
1477 dwc2_ep0_write(dev);
1480 dev->ep0state = DATA_STATE_RECV;