2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <usbroothubdes.h>
17 /* Use only HC channel 0. */
18 #define DWC2_HC_CHANNEL 0
20 #define DWC2_STATUS_BUF_SIZE 64
21 #define DWC2_DATA_BUF_SIZE (64 * 1024)
23 /* We need doubleword-aligned buffers for DMA transfers */
24 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer, DWC2_DATA_BUF_SIZE, 8);
25 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer, DWC2_STATUS_BUF_SIZE, 8);
28 #define MAX_ENDPOINT 16
29 static int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
30 static int control_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
32 static int root_hub_devnum;
34 static struct dwc2_core_regs *regs =
35 (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
40 static int wait_for_bit(void *reg, const uint32_t mask, bool set)
42 unsigned int timeout = 1000000;
50 if ((val & mask) == mask)
56 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
57 __func__, reg, mask, set);
63 * Initializes the FSLSPClkSel field of the HCFG register
64 * depending on the PHY type.
66 static void init_fslspclksel(struct dwc2_core_regs *regs)
70 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
71 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
73 /* High speed PHY running at full speed or high speed */
74 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
77 #ifdef CONFIG_DWC2_ULPI_FS_LS
78 uint32_t hwcfg2 = readl(®s->ghwcfg2);
79 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
80 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
81 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
82 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
84 if (hval == 2 && fval == 1)
85 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
88 clrsetbits_le32(®s->host_regs.hcfg,
89 DWC2_HCFG_FSLSPCLKSEL_MASK,
90 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
96 * @param regs Programming view of DWC_otg controller.
97 * @param num Tx FIFO to flush.
99 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
103 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
105 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
107 printf("%s: Timeout!\n", __func__);
109 /* Wait for 3 PHY Clocks */
116 * @param regs Programming view of DWC_otg controller.
118 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
122 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
123 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
125 printf("%s: Timeout!\n", __func__);
127 /* Wait for 3 PHY Clocks */
132 * Do core a soft reset of the core. Be careful with this because it
133 * resets all the internal state machines of the core.
135 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
139 /* Wait for AHB master IDLE state. */
140 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
142 printf("%s: Timeout!\n", __func__);
144 /* Core Soft Reset */
145 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
146 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_CSFTRST, 0);
148 printf("%s: Timeout!\n", __func__);
151 * Wait for core to come out of reset.
152 * NOTE: This long sleep is _very_ important, otherwise the core will
153 * not stay in host mode after a connector ID change!
159 * This function initializes the DWC_otg controller registers for
162 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
163 * request queues. Host channels are reset to ensure that they are ready for
164 * performing transfers.
166 * @param regs Programming view of DWC_otg controller
169 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
171 uint32_t nptxfifosize = 0;
172 uint32_t ptxfifosize = 0;
174 int i, ret, num_channels;
176 /* Restart the Phy Clock */
177 writel(0, ®s->pcgcctl);
179 /* Initialize Host Configuration Register */
180 init_fslspclksel(regs);
181 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
182 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
185 /* Configure data FIFO sizes */
186 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
187 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
189 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
191 /* Non-periodic Tx FIFO */
192 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
193 DWC2_FIFOSIZE_DEPTH_OFFSET;
194 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
195 DWC2_FIFOSIZE_STARTADDR_OFFSET;
196 writel(nptxfifosize, ®s->gnptxfsiz);
198 /* Periodic Tx FIFO */
199 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
200 DWC2_FIFOSIZE_DEPTH_OFFSET;
201 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
202 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
203 DWC2_FIFOSIZE_STARTADDR_OFFSET;
204 writel(ptxfifosize, ®s->hptxfsiz);
208 /* Clear Host Set HNP Enable in the OTG Control Register */
209 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
211 /* Make sure the FIFOs are flushed. */
212 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
213 dwc_otg_flush_rx_fifo(regs);
215 /* Flush out any leftover queued requests. */
216 num_channels = readl(®s->ghwcfg2);
217 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
218 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
221 for (i = 0; i < num_channels; i++)
222 clrsetbits_le32(®s->hc_regs[i].hcchar,
223 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
226 /* Halt all channels to put them into a known state. */
227 for (i = 0; i < num_channels; i++) {
228 clrsetbits_le32(®s->hc_regs[i].hcchar,
230 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
231 ret = wait_for_bit(®s->hc_regs[i].hcchar,
232 DWC2_HCCHAR_CHEN, 0);
234 printf("%s: Timeout!\n", __func__);
237 /* Turn on the vbus power. */
238 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
239 hprt0 = readl(®s->hprt0);
240 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
241 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
242 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
243 hprt0 |= DWC2_HPRT0_PRTPWR;
244 writel(hprt0, ®s->hprt0);
250 * This function initializes the DWC_otg controller registers and
251 * prepares the core for device mode or host mode operation.
253 * @param regs Programming view of the DWC_otg controller
255 static void dwc_otg_core_init(struct dwc2_core_regs *regs)
259 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
261 /* Common Initialization */
262 usbcfg = readl(®s->gusbcfg);
264 /* Program the ULPI External VBUS bit if needed */
265 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
266 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
268 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
271 /* Set external TS Dline pulsing */
272 #ifdef CONFIG_DWC2_TS_DLINE
273 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
275 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
277 writel(usbcfg, ®s->gusbcfg);
279 /* Reset the Controller */
280 dwc_otg_core_reset(regs);
283 * This programming sequence needs to happen in FS mode before
284 * any other programming occurs
286 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
287 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
288 /* If FS mode with FS PHY */
289 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
291 /* Reset after a PHY select */
292 dwc_otg_core_reset(regs);
295 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
296 * Also do this on HNP Dev/Host mode switches (done in dev_init
299 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
300 init_fslspclksel(regs);
302 #ifdef CONFIG_DWC2_I2C_ENABLE
303 /* Program GUSBCFG.OtgUtmifsSel to I2C */
304 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
306 /* Program GI2CCTL.I2CEn */
307 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN |
308 DWC2_GI2CCTL_I2CDEVADDR_MASK,
309 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
310 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN);
314 /* High speed PHY. */
317 * HS PHY parameters. These parameters are preserved during
318 * soft reset so only program the first time. Do a soft reset
319 * immediately after setting phyif.
321 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
322 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
324 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
325 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
326 usbcfg |= DWC2_GUSBCFG_DDRSEL;
328 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
330 } else { /* UTMI+ interface */
331 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
332 usbcfg |= DWC2_GUSBCFG_PHYIF;
336 writel(usbcfg, ®s->gusbcfg);
338 /* Reset after setting the PHY parameters */
339 dwc_otg_core_reset(regs);
342 usbcfg = readl(®s->gusbcfg);
343 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
344 #ifdef CONFIG_DWC2_ULPI_FS_LS
345 uint32_t hwcfg2 = readl(®s->ghwcfg2);
346 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
347 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
348 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
349 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
350 if (hval == 2 && fval == 1) {
351 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
352 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
355 writel(usbcfg, ®s->gusbcfg);
357 /* Program the GAHBCFG Register. */
358 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
359 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
361 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
362 while (brst_sz > 1) {
363 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
364 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
368 #ifdef CONFIG_DWC2_DMA_ENABLE
369 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
373 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
374 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
375 #ifdef CONFIG_DWC2_DMA_ENABLE
376 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
381 writel(ahbcfg, ®s->gahbcfg);
383 /* Program the GUSBCFG register for HNP/SRP. */
384 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
386 #ifdef CONFIG_DWC2_IC_USB_CAP
387 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
392 * Prepares a host channel for transferring packets to/from a specific
393 * endpoint. The HCCHARn register is set up with the characteristics specified
394 * in _hc. Host channel interrupts that may need to be serviced while this
395 * transfer is in progress are enabled.
397 * @param regs Programming view of DWC_otg controller
398 * @param hc Information needed to initialize the host channel
400 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
401 uint8_t dev_addr, uint8_t ep_num, uint8_t ep_is_in,
402 uint8_t ep_type, uint16_t max_packet)
404 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num];
405 const uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
406 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
407 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
408 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
409 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
411 /* Clear old interrupt conditions for this host channel. */
412 writel(0x3fff, &hc_regs->hcint);
415 * Program the HCCHARn register with the endpoint characteristics
416 * for the current transfer.
418 writel(hcchar, &hc_regs->hcchar);
420 /* Program the HCSPLIT register for SPLITs */
421 writel(0, &hc_regs->hcsplt);
425 * DWC2 to USB API interface
427 /* Direction: In ; Request: Status */
428 static int dwc_otg_submit_rh_msg_in_status(struct usb_device *dev, void *buffer,
429 int txlen, struct devrequest *cmd)
432 uint32_t port_status = 0;
433 uint32_t port_change = 0;
437 switch (cmd->requesttype & ~USB_DIR_IN) {
439 *(uint16_t *)buffer = cpu_to_le16(1);
442 case USB_RECIP_INTERFACE:
443 case USB_RECIP_ENDPOINT:
444 *(uint16_t *)buffer = cpu_to_le16(0);
448 *(uint32_t *)buffer = cpu_to_le32(0);
451 case USB_RECIP_OTHER | USB_TYPE_CLASS:
452 hprt0 = readl(®s->hprt0);
453 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
454 port_status |= USB_PORT_STAT_CONNECTION;
455 if (hprt0 & DWC2_HPRT0_PRTENA)
456 port_status |= USB_PORT_STAT_ENABLE;
457 if (hprt0 & DWC2_HPRT0_PRTSUSP)
458 port_status |= USB_PORT_STAT_SUSPEND;
459 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
460 port_status |= USB_PORT_STAT_OVERCURRENT;
461 if (hprt0 & DWC2_HPRT0_PRTRST)
462 port_status |= USB_PORT_STAT_RESET;
463 if (hprt0 & DWC2_HPRT0_PRTPWR)
464 port_status |= USB_PORT_STAT_POWER;
466 port_status |= USB_PORT_STAT_HIGH_SPEED;
468 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
469 port_change |= USB_PORT_STAT_C_ENABLE;
470 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
471 port_change |= USB_PORT_STAT_C_CONNECTION;
472 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
473 port_change |= USB_PORT_STAT_C_OVERCURRENT;
475 *(uint32_t *)buffer = cpu_to_le32(port_status |
476 (port_change << 16));
480 puts("unsupported root hub command\n");
481 stat = USB_ST_STALLED;
484 dev->act_len = min(len, txlen);
490 /* Direction: In ; Request: Descriptor */
491 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
492 void *buffer, int txlen,
493 struct devrequest *cmd)
495 unsigned char data[32];
499 uint16_t wValue = cpu_to_le16(cmd->value);
500 uint16_t wLength = cpu_to_le16(cmd->length);
502 switch (cmd->requesttype & ~USB_DIR_IN) {
504 switch (wValue & 0xff00) {
505 case 0x0100: /* device descriptor */
506 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
507 memcpy(buffer, root_hub_dev_des, len);
509 case 0x0200: /* configuration descriptor */
510 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
511 memcpy(buffer, root_hub_config_des, len);
513 case 0x0300: /* string descriptors */
514 switch (wValue & 0xff) {
516 len = min3(txlen, (int)sizeof(root_hub_str_index0),
518 memcpy(buffer, root_hub_str_index0, len);
521 len = min3(txlen, (int)sizeof(root_hub_str_index1),
523 memcpy(buffer, root_hub_str_index1, len);
528 stat = USB_ST_STALLED;
533 /* Root port config, set 1 port and nothing else. */
536 data[0] = 9; /* min length; */
538 data[2] = dsc & RH_A_NDP;
544 else if (dsc & RH_A_OCPM)
547 /* corresponds to data[4-7] */
548 data[5] = (dsc & RH_A_POTPGT) >> 24;
549 data[7] = dsc & RH_B_DR;
554 data[8] = (dsc & RH_B_DR) >> 8;
559 len = min3(txlen, (int)data[0], (int)wLength);
560 memcpy(buffer, data, len);
563 puts("unsupported root hub command\n");
564 stat = USB_ST_STALLED;
567 dev->act_len = min(len, txlen);
573 /* Direction: In ; Request: Configuration */
574 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
575 void *buffer, int txlen,
576 struct devrequest *cmd)
581 switch (cmd->requesttype & ~USB_DIR_IN) {
583 *(uint8_t *)buffer = 0x01;
587 puts("unsupported root hub command\n");
588 stat = USB_ST_STALLED;
591 dev->act_len = min(len, txlen);
598 static int dwc_otg_submit_rh_msg_in(struct usb_device *dev,
599 void *buffer, int txlen,
600 struct devrequest *cmd)
602 switch (cmd->request) {
603 case USB_REQ_GET_STATUS:
604 return dwc_otg_submit_rh_msg_in_status(dev, buffer,
606 case USB_REQ_GET_DESCRIPTOR:
607 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
609 case USB_REQ_GET_CONFIGURATION:
610 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
613 puts("unsupported root hub command\n");
614 return USB_ST_STALLED;
619 static int dwc_otg_submit_rh_msg_out(struct usb_device *dev,
620 void *buffer, int txlen,
621 struct devrequest *cmd)
625 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
626 uint16_t wValue = cpu_to_le16(cmd->value);
628 switch (bmrtype_breq & ~USB_DIR_IN) {
629 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
630 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
633 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
635 case USB_PORT_FEAT_C_CONNECTION:
636 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET);
641 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
643 case USB_PORT_FEAT_SUSPEND:
646 case USB_PORT_FEAT_RESET:
647 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
648 DWC2_HPRT0_PRTCONNDET |
649 DWC2_HPRT0_PRTENCHNG |
650 DWC2_HPRT0_PRTOVRCURRCHNG,
653 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST);
656 case USB_PORT_FEAT_POWER:
657 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
658 DWC2_HPRT0_PRTCONNDET |
659 DWC2_HPRT0_PRTENCHNG |
660 DWC2_HPRT0_PRTOVRCURRCHNG,
664 case USB_PORT_FEAT_ENABLE:
668 case (USB_REQ_SET_ADDRESS << 8):
669 root_hub_devnum = wValue;
671 case (USB_REQ_SET_CONFIGURATION << 8):
674 puts("unsupported root hub command\n");
675 stat = USB_ST_STALLED;
678 len = min(len, txlen);
686 static int dwc_otg_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
687 void *buffer, int txlen,
688 struct devrequest *cmd)
692 if (usb_pipeint(pipe)) {
693 puts("Root-Hub submit IRQ: NOT implemented\n");
697 if (cmd->requesttype & USB_DIR_IN)
698 stat = dwc_otg_submit_rh_msg_in(dev, buffer, txlen, cmd);
700 stat = dwc_otg_submit_rh_msg_out(dev, buffer, txlen, cmd);
707 int wait_for_chhltd(uint32_t *sub, int *toggle)
709 const uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP |
710 DWC2_HCINT_CHHLTD | DWC2_HCINT_ACK;
711 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
713 uint32_t hcint, hctsiz;
715 ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true);
719 hcint = readl(&hc_regs->hcint);
720 if (hcint != hcint_comp_hlt_ack) {
721 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
725 hctsiz = readl(&hc_regs->hctsiz);
726 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
727 DWC2_HCTSIZ_XFERSIZE_OFFSET;
729 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >>
730 DWC2_HCTSIZ_PID_OFFSET;
732 debug("%s: sub=%u toggle=%d\n", __func__, *sub, toggle ? *toggle : -1);
737 /* U-Boot USB transmission interface */
738 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
741 int devnum = usb_pipedevice(pipe);
742 int ep = usb_pipeendpoint(pipe);
743 int max = usb_maxpacket(dev, pipe);
747 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
749 uint32_t num_packets;
750 int stop_transfer = 0;
752 if (devnum == root_hub_devnum) {
757 if (len > DWC2_DATA_BUF_SIZE) {
758 printf("%s: %d is more then available buffer size (%d)\n",
759 __func__, len, DWC2_DATA_BUF_SIZE);
765 while ((done < len) && !stop_transfer) {
766 /* Initialize channel */
767 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep,
768 usb_pipein(pipe), DWC2_HCCHAR_EPTYPE_BULK, max);
770 xfer_len = len - done;
771 /* Make sure that xfer_len is a multiple of max packet size. */
772 if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
773 xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1;
776 num_packets = (xfer_len + max - 1) / max;
777 if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) {
778 num_packets = CONFIG_DWC2_MAX_PACKET_COUNT;
779 xfer_len = num_packets * max;
785 if (usb_pipein(pipe))
786 xfer_len = num_packets * max;
788 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
789 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
790 (bulk_data_toggle[devnum][ep] <<
791 DWC2_HCTSIZ_PID_OFFSET),
794 memcpy(aligned_buffer, (char *)buffer + done, len - done);
795 writel((uint32_t)aligned_buffer, &hc_regs->hcdma);
797 /* Set host channel enable after all other setup is complete. */
798 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
799 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
800 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
803 ret = wait_for_chhltd(&sub, &bulk_data_toggle[devnum][ep]);
810 if (usb_pipein(pipe)) {
817 if (done && usb_pipein(pipe))
818 memcpy(buffer, aligned_buffer, done);
820 writel(0, &hc_regs->hcintmsk);
821 writel(0xFFFFFFFF, &hc_regs->hcint);
829 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
830 int len, struct devrequest *setup)
832 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
834 int devnum = usb_pipedevice(pipe);
835 int ep = usb_pipeendpoint(pipe);
836 int max = usb_maxpacket(dev, pipe);
840 /* For CONTROL endpoint pid should start with DATA1 */
841 int status_direction;
843 if (devnum == root_hub_devnum) {
845 dev->speed = USB_SPEED_HIGH;
846 return dwc_otg_submit_rh_msg(dev, pipe, buffer, len, setup);
849 if (len > DWC2_DATA_BUF_SIZE) {
850 printf("%s: %d is more then available buffer size(%d)\n",
851 __func__, len, DWC2_DATA_BUF_SIZE);
857 /* Initialize channel, OUT for setup buffer */
858 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep, 0,
859 DWC2_HCCHAR_EPTYPE_CONTROL, max);
862 writel((8 << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
863 (1 << DWC2_HCTSIZ_PKTCNT_OFFSET) |
864 (DWC2_HC_PID_SETUP << DWC2_HCTSIZ_PID_OFFSET),
867 writel((uint32_t)setup, &hc_regs->hcdma);
869 /* Set host channel enable after all other setup is complete. */
870 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
871 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
872 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | DWC2_HCCHAR_CHEN);
874 ret = wait_for_chhltd(&sub, NULL);
881 /* Clear interrupts */
882 writel(0, &hc_regs->hcintmsk);
883 writel(0xFFFFFFFF, &hc_regs->hcint);
887 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep,
889 DWC2_HCCHAR_EPTYPE_CONTROL, max);
891 /* TODO: check if len < 64 */
892 control_data_toggle[devnum][ep] = DWC2_HC_PID_DATA1;
893 writel((len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
894 (1 << DWC2_HCTSIZ_PKTCNT_OFFSET) |
895 (control_data_toggle[devnum][ep] <<
896 DWC2_HCTSIZ_PID_OFFSET),
899 writel((uint32_t)buffer, &hc_regs->hcdma);
901 /* Set host channel enable after all other setup is complete */
902 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
903 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
904 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
907 ret = wait_for_chhltd(&sub, &control_data_toggle[devnum][ep]);
915 if (usb_pipein(pipe))
917 } /* End of DATA stage */
920 if ((len == 0) || usb_pipeout(pipe))
921 status_direction = 1;
923 status_direction = 0;
925 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep,
926 status_direction, DWC2_HCCHAR_EPTYPE_CONTROL, max);
928 writel((1 << DWC2_HCTSIZ_PKTCNT_OFFSET) |
929 (DWC2_HC_PID_DATA1 << DWC2_HCTSIZ_PID_OFFSET),
932 writel((uint32_t)status_buffer, &hc_regs->hcdma);
934 /* Set host channel enable after all other setup is complete. */
935 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
936 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
937 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | DWC2_HCCHAR_CHEN);
939 ret = wait_for_chhltd(&sub, NULL);
952 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
953 int len, int interval)
955 printf("dev = %p pipe = %#lx buf = %p size = %d int = %d\n",
956 dev, pipe, buffer, len, interval);
960 /* U-Boot USB control interface */
961 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
968 snpsid = readl(®s->gsnpsid);
969 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
971 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx) {
972 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
976 dwc_otg_core_init(regs);
977 dwc_otg_core_host_init(regs);
979 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
980 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
981 DWC2_HPRT0_PRTOVRCURRCHNG,
984 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
985 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
988 for (i = 0; i < MAX_DEVICE; i++) {
989 for (j = 0; j < MAX_ENDPOINT; j++) {
990 control_data_toggle[i][j] = DWC2_HC_PID_DATA1;
991 bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
998 int usb_lowlevel_stop(int index)
1000 /* Put everything in reset. */
1001 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1002 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1003 DWC2_HPRT0_PRTOVRCURRCHNG,