2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <usbroothubdes.h>
20 /* Use only HC channel 0. */
21 #define DWC2_HC_CHANNEL 0
23 #define DWC2_STATUS_BUF_SIZE 64
24 #define DWC2_DATA_BUF_SIZE (64 * 1024)
27 #define MAX_ENDPOINT 16
31 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
32 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
34 uint8_t *aligned_buffer;
35 uint8_t *status_buffer;
37 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
38 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
39 struct dwc2_core_regs *regs;
44 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
45 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
47 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
50 static struct dwc2_priv local;
56 static int wait_for_bit(void *reg, const uint32_t mask, bool set)
58 unsigned int timeout = 1000000;
66 if ((val & mask) == mask)
72 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
73 __func__, reg, mask, set);
79 * Initializes the FSLSPClkSel field of the HCFG register
80 * depending on the PHY type.
82 static void init_fslspclksel(struct dwc2_core_regs *regs)
86 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
87 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
89 /* High speed PHY running at full speed or high speed */
90 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
93 #ifdef CONFIG_DWC2_ULPI_FS_LS
94 uint32_t hwcfg2 = readl(®s->ghwcfg2);
95 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
96 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
97 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
98 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
100 if (hval == 2 && fval == 1)
101 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
104 clrsetbits_le32(®s->host_regs.hcfg,
105 DWC2_HCFG_FSLSPCLKSEL_MASK,
106 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
112 * @param regs Programming view of DWC_otg controller.
113 * @param num Tx FIFO to flush.
115 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
119 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
121 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
123 printf("%s: Timeout!\n", __func__);
125 /* Wait for 3 PHY Clocks */
132 * @param regs Programming view of DWC_otg controller.
134 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
138 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
139 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
141 printf("%s: Timeout!\n", __func__);
143 /* Wait for 3 PHY Clocks */
148 * Do core a soft reset of the core. Be careful with this because it
149 * resets all the internal state machines of the core.
151 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
155 /* Wait for AHB master IDLE state. */
156 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
158 printf("%s: Timeout!\n", __func__);
160 /* Core Soft Reset */
161 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
162 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_CSFTRST, 0);
164 printf("%s: Timeout!\n", __func__);
167 * Wait for core to come out of reset.
168 * NOTE: This long sleep is _very_ important, otherwise the core will
169 * not stay in host mode after a connector ID change!
175 * This function initializes the DWC_otg controller registers for
178 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
179 * request queues. Host channels are reset to ensure that they are ready for
180 * performing transfers.
182 * @param regs Programming view of DWC_otg controller
185 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
187 uint32_t nptxfifosize = 0;
188 uint32_t ptxfifosize = 0;
190 int i, ret, num_channels;
192 /* Restart the Phy Clock */
193 writel(0, ®s->pcgcctl);
195 /* Initialize Host Configuration Register */
196 init_fslspclksel(regs);
197 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
198 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
201 /* Configure data FIFO sizes */
202 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
203 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
205 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
207 /* Non-periodic Tx FIFO */
208 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
209 DWC2_FIFOSIZE_DEPTH_OFFSET;
210 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
211 DWC2_FIFOSIZE_STARTADDR_OFFSET;
212 writel(nptxfifosize, ®s->gnptxfsiz);
214 /* Periodic Tx FIFO */
215 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
216 DWC2_FIFOSIZE_DEPTH_OFFSET;
217 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
218 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
219 DWC2_FIFOSIZE_STARTADDR_OFFSET;
220 writel(ptxfifosize, ®s->hptxfsiz);
224 /* Clear Host Set HNP Enable in the OTG Control Register */
225 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
227 /* Make sure the FIFOs are flushed. */
228 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
229 dwc_otg_flush_rx_fifo(regs);
231 /* Flush out any leftover queued requests. */
232 num_channels = readl(®s->ghwcfg2);
233 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
234 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
237 for (i = 0; i < num_channels; i++)
238 clrsetbits_le32(®s->hc_regs[i].hcchar,
239 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
242 /* Halt all channels to put them into a known state. */
243 for (i = 0; i < num_channels; i++) {
244 clrsetbits_le32(®s->hc_regs[i].hcchar,
246 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
247 ret = wait_for_bit(®s->hc_regs[i].hcchar,
248 DWC2_HCCHAR_CHEN, 0);
250 printf("%s: Timeout!\n", __func__);
253 /* Turn on the vbus power. */
254 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
255 hprt0 = readl(®s->hprt0);
256 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
257 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
258 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
259 hprt0 |= DWC2_HPRT0_PRTPWR;
260 writel(hprt0, ®s->hprt0);
266 * This function initializes the DWC_otg controller registers and
267 * prepares the core for device mode or host mode operation.
269 * @param regs Programming view of the DWC_otg controller
271 static void dwc_otg_core_init(struct dwc2_core_regs *regs)
275 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
277 /* Common Initialization */
278 usbcfg = readl(®s->gusbcfg);
280 /* Program the ULPI External VBUS bit if needed */
281 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
282 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
284 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
287 /* Set external TS Dline pulsing */
288 #ifdef CONFIG_DWC2_TS_DLINE
289 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
291 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
293 writel(usbcfg, ®s->gusbcfg);
295 /* Reset the Controller */
296 dwc_otg_core_reset(regs);
299 * This programming sequence needs to happen in FS mode before
300 * any other programming occurs
302 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
303 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
304 /* If FS mode with FS PHY */
305 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
307 /* Reset after a PHY select */
308 dwc_otg_core_reset(regs);
311 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
312 * Also do this on HNP Dev/Host mode switches (done in dev_init
315 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
316 init_fslspclksel(regs);
318 #ifdef CONFIG_DWC2_I2C_ENABLE
319 /* Program GUSBCFG.OtgUtmifsSel to I2C */
320 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
322 /* Program GI2CCTL.I2CEn */
323 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN |
324 DWC2_GI2CCTL_I2CDEVADDR_MASK,
325 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
326 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN);
330 /* High speed PHY. */
333 * HS PHY parameters. These parameters are preserved during
334 * soft reset so only program the first time. Do a soft reset
335 * immediately after setting phyif.
337 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
338 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
340 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
341 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
342 usbcfg |= DWC2_GUSBCFG_DDRSEL;
344 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
346 } else { /* UTMI+ interface */
347 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
348 usbcfg |= DWC2_GUSBCFG_PHYIF;
352 writel(usbcfg, ®s->gusbcfg);
354 /* Reset after setting the PHY parameters */
355 dwc_otg_core_reset(regs);
358 usbcfg = readl(®s->gusbcfg);
359 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
360 #ifdef CONFIG_DWC2_ULPI_FS_LS
361 uint32_t hwcfg2 = readl(®s->ghwcfg2);
362 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
363 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
364 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
365 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
366 if (hval == 2 && fval == 1) {
367 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
368 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
371 writel(usbcfg, ®s->gusbcfg);
373 /* Program the GAHBCFG Register. */
374 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
375 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
377 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
378 while (brst_sz > 1) {
379 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
380 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
384 #ifdef CONFIG_DWC2_DMA_ENABLE
385 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
389 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
390 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
391 #ifdef CONFIG_DWC2_DMA_ENABLE
392 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
397 writel(ahbcfg, ®s->gahbcfg);
399 /* Program the GUSBCFG register for HNP/SRP. */
400 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
402 #ifdef CONFIG_DWC2_IC_USB_CAP
403 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
408 * Prepares a host channel for transferring packets to/from a specific
409 * endpoint. The HCCHARn register is set up with the characteristics specified
410 * in _hc. Host channel interrupts that may need to be serviced while this
411 * transfer is in progress are enabled.
413 * @param regs Programming view of DWC_otg controller
414 * @param hc Information needed to initialize the host channel
416 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
417 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
418 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
420 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num];
421 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
422 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
423 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
424 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
425 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
427 if (dev->speed == USB_SPEED_LOW)
428 hcchar |= DWC2_HCCHAR_LSPDDEV;
431 * Program the HCCHARn register with the endpoint characteristics
432 * for the current transfer.
434 writel(hcchar, &hc_regs->hcchar);
436 /* Program the HCSPLIT register, default to no SPLIT */
437 writel(0, &hc_regs->hcsplt);
440 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
441 uint8_t hub_devnum, uint8_t hub_port)
445 hcsplt = DWC2_HCSPLT_SPLTENA;
446 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
447 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
449 /* Program the HCSPLIT register for SPLITs */
450 writel(hcsplt, &hc_regs->hcsplt);
454 * DWC2 to USB API interface
456 /* Direction: In ; Request: Status */
457 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
458 struct usb_device *dev, void *buffer,
459 int txlen, struct devrequest *cmd)
462 uint32_t port_status = 0;
463 uint32_t port_change = 0;
467 switch (cmd->requesttype & ~USB_DIR_IN) {
469 *(uint16_t *)buffer = cpu_to_le16(1);
472 case USB_RECIP_INTERFACE:
473 case USB_RECIP_ENDPOINT:
474 *(uint16_t *)buffer = cpu_to_le16(0);
478 *(uint32_t *)buffer = cpu_to_le32(0);
481 case USB_RECIP_OTHER | USB_TYPE_CLASS:
482 hprt0 = readl(®s->hprt0);
483 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
484 port_status |= USB_PORT_STAT_CONNECTION;
485 if (hprt0 & DWC2_HPRT0_PRTENA)
486 port_status |= USB_PORT_STAT_ENABLE;
487 if (hprt0 & DWC2_HPRT0_PRTSUSP)
488 port_status |= USB_PORT_STAT_SUSPEND;
489 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
490 port_status |= USB_PORT_STAT_OVERCURRENT;
491 if (hprt0 & DWC2_HPRT0_PRTRST)
492 port_status |= USB_PORT_STAT_RESET;
493 if (hprt0 & DWC2_HPRT0_PRTPWR)
494 port_status |= USB_PORT_STAT_POWER;
496 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
497 port_status |= USB_PORT_STAT_LOW_SPEED;
498 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
499 DWC2_HPRT0_PRTSPD_HIGH)
500 port_status |= USB_PORT_STAT_HIGH_SPEED;
502 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
503 port_change |= USB_PORT_STAT_C_ENABLE;
504 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
505 port_change |= USB_PORT_STAT_C_CONNECTION;
506 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
507 port_change |= USB_PORT_STAT_C_OVERCURRENT;
509 *(uint32_t *)buffer = cpu_to_le32(port_status |
510 (port_change << 16));
514 puts("unsupported root hub command\n");
515 stat = USB_ST_STALLED;
518 dev->act_len = min(len, txlen);
524 /* Direction: In ; Request: Descriptor */
525 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
526 void *buffer, int txlen,
527 struct devrequest *cmd)
529 unsigned char data[32];
533 uint16_t wValue = cpu_to_le16(cmd->value);
534 uint16_t wLength = cpu_to_le16(cmd->length);
536 switch (cmd->requesttype & ~USB_DIR_IN) {
538 switch (wValue & 0xff00) {
539 case 0x0100: /* device descriptor */
540 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
541 memcpy(buffer, root_hub_dev_des, len);
543 case 0x0200: /* configuration descriptor */
544 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
545 memcpy(buffer, root_hub_config_des, len);
547 case 0x0300: /* string descriptors */
548 switch (wValue & 0xff) {
550 len = min3(txlen, (int)sizeof(root_hub_str_index0),
552 memcpy(buffer, root_hub_str_index0, len);
555 len = min3(txlen, (int)sizeof(root_hub_str_index1),
557 memcpy(buffer, root_hub_str_index1, len);
562 stat = USB_ST_STALLED;
567 /* Root port config, set 1 port and nothing else. */
570 data[0] = 9; /* min length; */
572 data[2] = dsc & RH_A_NDP;
578 else if (dsc & RH_A_OCPM)
581 /* corresponds to data[4-7] */
582 data[5] = (dsc & RH_A_POTPGT) >> 24;
583 data[7] = dsc & RH_B_DR;
588 data[8] = (dsc & RH_B_DR) >> 8;
593 len = min3(txlen, (int)data[0], (int)wLength);
594 memcpy(buffer, data, len);
597 puts("unsupported root hub command\n");
598 stat = USB_ST_STALLED;
601 dev->act_len = min(len, txlen);
607 /* Direction: In ; Request: Configuration */
608 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
609 void *buffer, int txlen,
610 struct devrequest *cmd)
615 switch (cmd->requesttype & ~USB_DIR_IN) {
617 *(uint8_t *)buffer = 0x01;
621 puts("unsupported root hub command\n");
622 stat = USB_ST_STALLED;
625 dev->act_len = min(len, txlen);
632 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
633 struct usb_device *dev, void *buffer,
634 int txlen, struct devrequest *cmd)
636 switch (cmd->request) {
637 case USB_REQ_GET_STATUS:
638 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
640 case USB_REQ_GET_DESCRIPTOR:
641 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
643 case USB_REQ_GET_CONFIGURATION:
644 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
647 puts("unsupported root hub command\n");
648 return USB_ST_STALLED;
653 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
654 struct usb_device *dev,
655 void *buffer, int txlen,
656 struct devrequest *cmd)
658 struct dwc2_core_regs *regs = priv->regs;
661 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
662 uint16_t wValue = cpu_to_le16(cmd->value);
664 switch (bmrtype_breq & ~USB_DIR_IN) {
665 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
666 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
669 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
671 case USB_PORT_FEAT_C_CONNECTION:
672 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET);
677 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
679 case USB_PORT_FEAT_SUSPEND:
682 case USB_PORT_FEAT_RESET:
683 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
684 DWC2_HPRT0_PRTCONNDET |
685 DWC2_HPRT0_PRTENCHNG |
686 DWC2_HPRT0_PRTOVRCURRCHNG,
689 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST);
692 case USB_PORT_FEAT_POWER:
693 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
694 DWC2_HPRT0_PRTCONNDET |
695 DWC2_HPRT0_PRTENCHNG |
696 DWC2_HPRT0_PRTOVRCURRCHNG,
700 case USB_PORT_FEAT_ENABLE:
704 case (USB_REQ_SET_ADDRESS << 8):
705 priv->root_hub_devnum = wValue;
707 case (USB_REQ_SET_CONFIGURATION << 8):
710 puts("unsupported root hub command\n");
711 stat = USB_ST_STALLED;
714 len = min(len, txlen);
722 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
723 unsigned long pipe, void *buffer, int txlen,
724 struct devrequest *cmd)
728 if (usb_pipeint(pipe)) {
729 puts("Root-Hub submit IRQ: NOT implemented\n");
733 if (cmd->requesttype & USB_DIR_IN)
734 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
736 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
743 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
746 uint32_t hcint, hctsiz;
748 ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true);
752 hcint = readl(&hc_regs->hcint);
753 hctsiz = readl(&hc_regs->hctsiz);
754 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
755 DWC2_HCTSIZ_XFERSIZE_OFFSET;
756 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
758 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
761 if (hcint & DWC2_HCINT_XFERCOMP)
764 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
767 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
771 static int dwc2_eptype[] = {
772 DWC2_HCCHAR_EPTYPE_ISOC,
773 DWC2_HCCHAR_EPTYPE_INTR,
774 DWC2_HCCHAR_EPTYPE_CONTROL,
775 DWC2_HCCHAR_EPTYPE_BULK,
778 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
779 u8 *pid, int in, void *buffer, int num_packets,
780 int xfer_len, int *actual_len, int odd_frame)
785 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
786 *pid, xfer_len, num_packets);
788 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
789 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
790 (*pid << DWC2_HCTSIZ_PID_OFFSET),
793 if (!in && xfer_len) {
794 memcpy(aligned_buffer, buffer, xfer_len);
796 flush_dcache_range((unsigned long)aligned_buffer,
797 (unsigned long)aligned_buffer +
798 roundup(xfer_len, ARCH_DMA_MINALIGN));
801 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
803 /* Clear old interrupt conditions for this host channel. */
804 writel(0x3fff, &hc_regs->hcint);
806 /* Set host channel enable after all other setup is complete. */
807 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
808 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
810 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
811 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
814 ret = wait_for_chhltd(hc_regs, &sub, pid);
821 invalidate_dcache_range((unsigned long)aligned_buffer,
822 (unsigned long)aligned_buffer +
823 roundup(xfer_len, ARCH_DMA_MINALIGN));
825 memcpy(buffer, aligned_buffer, xfer_len);
827 *actual_len = xfer_len;
832 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
833 unsigned long pipe, u8 *pid, int in, void *buffer, int len)
835 struct dwc2_core_regs *regs = priv->regs;
836 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
837 struct dwc2_host_regs *host_regs = ®s->host_regs;
838 int devnum = usb_pipedevice(pipe);
839 int ep = usb_pipeendpoint(pipe);
840 int max = usb_maxpacket(dev, pipe);
841 int eptype = dwc2_eptype[usb_pipetype(pipe)];
845 int complete_split = 0;
847 uint32_t num_packets;
848 int stop_transfer = 0;
849 uint32_t max_xfer_len;
850 int ssplit_frame_num = 0;
852 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
855 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
856 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
857 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
858 if (max_xfer_len > DWC2_DATA_BUF_SIZE)
859 max_xfer_len = DWC2_DATA_BUF_SIZE;
861 /* Make sure that max_xfer_len is a multiple of max packet size. */
862 num_packets = max_xfer_len / max;
863 max_xfer_len = num_packets * max;
865 /* Initialize channel */
866 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
869 /* Check if the target is a FS/LS device behind a HS hub */
870 if (dev->speed != USB_SPEED_HIGH) {
873 uint32_t hprt0 = readl(®s->hprt0);
874 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
875 DWC2_HPRT0_PRTSPD_HIGH) {
876 usb_find_usb2_hub_address_port(dev, &hub_addr,
878 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
890 xfer_len = len - done;
892 if (xfer_len > max_xfer_len)
893 xfer_len = max_xfer_len;
894 else if (xfer_len > max)
895 num_packets = (xfer_len + max - 1) / max;
900 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
902 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
904 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
905 int uframe_num = readl(&host_regs->hfnum);
906 if (!(uframe_num & 0x1))
910 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
911 in, (char *)buffer + done, num_packets,
912 xfer_len, &actual_len, odd_frame);
914 hcint = readl(&hc_regs->hcint);
915 if (complete_split) {
917 if (hcint & DWC2_HCINT_NYET) {
919 int frame_num = DWC2_HFNUM_MAX_FRNUM &
920 readl(&host_regs->hfnum);
921 if (((frame_num - ssplit_frame_num) &
922 DWC2_HFNUM_MAX_FRNUM) > 4)
926 } else if (do_split) {
927 if (hcint & DWC2_HCINT_ACK) {
928 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
929 readl(&host_regs->hfnum);
938 if (actual_len < xfer_len)
943 /* Transactions are done when when either all data is transferred or
944 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
947 } while (((done < len) && !stop_transfer) || complete_split);
949 writel(0, &hc_regs->hcintmsk);
950 writel(0xFFFFFFFF, &hc_regs->hcint);
958 /* U-Boot USB transmission interface */
959 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
960 unsigned long pipe, void *buffer, int len)
962 int devnum = usb_pipedevice(pipe);
963 int ep = usb_pipeendpoint(pipe);
966 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
971 if (usb_pipein(pipe))
972 pid = &priv->in_data_toggle[devnum][ep];
974 pid = &priv->out_data_toggle[devnum][ep];
976 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
979 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
980 unsigned long pipe, void *buffer, int len,
981 struct devrequest *setup)
983 int devnum = usb_pipedevice(pipe);
986 /* For CONTROL endpoint pid should start with DATA1 */
987 int status_direction;
989 if (devnum == priv->root_hub_devnum) {
991 dev->speed = USB_SPEED_HIGH;
992 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
997 pid = DWC2_HC_PID_SETUP;
999 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1000 } while (ret == -EAGAIN);
1007 pid = DWC2_HC_PID_DATA1;
1009 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1011 act_len += dev->act_len;
1012 buffer += dev->act_len;
1013 len -= dev->act_len;
1014 } while (ret == -EAGAIN);
1017 status_direction = usb_pipeout(pipe);
1019 /* No-data CONTROL always ends with an IN transaction */
1020 status_direction = 1;
1024 pid = DWC2_HC_PID_DATA1;
1026 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1027 priv->status_buffer, 0);
1028 } while (ret == -EAGAIN);
1032 dev->act_len = act_len;
1037 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1038 unsigned long pipe, void *buffer, int len, int interval)
1040 unsigned long timeout;
1043 /* FIXME: what is interval? */
1045 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1047 if (get_timer(0) > timeout) {
1048 printf("Timeout poll on interrupt endpoint\n");
1051 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1057 static int dwc2_init_common(struct dwc2_priv *priv)
1059 struct dwc2_core_regs *regs = priv->regs;
1063 snpsid = readl(®s->gsnpsid);
1064 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
1066 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1067 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1068 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
1072 dwc_otg_core_init(regs);
1073 dwc_otg_core_host_init(regs);
1075 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1076 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1077 DWC2_HPRT0_PRTOVRCURRCHNG,
1080 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1081 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1084 for (i = 0; i < MAX_DEVICE; i++) {
1085 for (j = 0; j < MAX_ENDPOINT; j++) {
1086 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1087 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1094 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1096 /* Put everything in reset. */
1097 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1098 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1099 DWC2_HPRT0_PRTOVRCURRCHNG,
1103 #ifndef CONFIG_DM_USB
1104 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1105 int len, struct devrequest *setup)
1107 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1110 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1113 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1116 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1117 int len, int interval)
1119 return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
1122 /* U-Boot USB control interface */
1123 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1125 struct dwc2_priv *priv = &local;
1127 memset(priv, '\0', sizeof(*priv));
1128 priv->root_hub_devnum = 0;
1129 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1130 priv->aligned_buffer = aligned_buffer_addr;
1131 priv->status_buffer = status_buffer_addr;
1133 /* board-dependant init */
1134 if (board_usb_init(index, USB_INIT_HOST))
1137 return dwc2_init_common(priv);
1140 int usb_lowlevel_stop(int index)
1142 dwc2_uninit_common(local.regs);
1148 #ifdef CONFIG_DM_USB
1149 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1150 unsigned long pipe, void *buffer, int length,
1151 struct devrequest *setup)
1153 struct dwc2_priv *priv = dev_get_priv(dev);
1155 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1156 dev->name, udev, udev->dev->name, udev->portnr);
1158 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1161 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1162 unsigned long pipe, void *buffer, int length)
1164 struct dwc2_priv *priv = dev_get_priv(dev);
1166 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1168 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1171 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1172 unsigned long pipe, void *buffer, int length,
1175 struct dwc2_priv *priv = dev_get_priv(dev);
1177 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1179 return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
1182 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1184 struct dwc2_priv *priv = dev_get_priv(dev);
1187 addr = dev_get_addr(dev);
1188 if (addr == FDT_ADDR_T_NONE)
1190 priv->regs = (struct dwc2_core_regs *)addr;
1195 static int dwc2_usb_probe(struct udevice *dev)
1197 struct dwc2_priv *priv = dev_get_priv(dev);
1199 return dwc2_init_common(priv);
1202 static int dwc2_usb_remove(struct udevice *dev)
1204 struct dwc2_priv *priv = dev_get_priv(dev);
1206 dwc2_uninit_common(priv->regs);
1211 struct dm_usb_ops dwc2_usb_ops = {
1212 .control = dwc2_submit_control_msg,
1213 .bulk = dwc2_submit_bulk_msg,
1214 .interrupt = dwc2_submit_int_msg,
1217 static const struct udevice_id dwc2_usb_ids[] = {
1218 { .compatible = "brcm,bcm2835-usb" },
1219 { .compatible = "snps,dwc2" },
1223 U_BOOT_DRIVER(usb_dwc2) = {
1226 .of_match = dwc2_usb_ids,
1227 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1228 .probe = dwc2_usb_probe,
1229 .remove = dwc2_usb_remove,
1230 .ops = &dwc2_usb_ops,
1231 .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1232 .flags = DM_FLAG_ALLOC_PRIV_DMA,