git.sur5r.net Git - u-boot/blob - drivers/usb/host/dwc2.c

   1 /*
   2  * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
   3  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <errno.h>
  10 #include <usb.h>
  11 #include <malloc.h>
  12 #include <phys2bus.h>
  13 #include <usbroothubdes.h>
  14 #include <asm/io.h>
  15
  16 #include "dwc2.h"
  17
  18 /* Use only HC channel 0. */
  19 #define DWC2_HC_CHANNEL                 0
  20
  21 #define DWC2_STATUS_BUF_SIZE            64
  22 #define DWC2_DATA_BUF_SIZE              (64 * 1024)
  23
  24 /* We need doubleword-aligned buffers for DMA transfers */
  25 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer, DWC2_DATA_BUF_SIZE, 8);
  26 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer, DWC2_STATUS_BUF_SIZE, 8);
  27
  28 #define MAX_DEVICE                      16
  29 #define MAX_ENDPOINT                    16
  30 static int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  31
  32 static int root_hub_devnum;
  33
  34 static struct dwc2_core_regs *regs =
  35         (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
  36
  37 /*
  38  * DWC2 IP interface
  39  */
  40 static int wait_for_bit(void *reg, const uint32_t mask, bool set)
  41 {
  42         unsigned int timeout = 1000000;
  43         uint32_t val;
  44
  45         while (--timeout) {
  46                 val = readl(reg);
  47                 if (!set)
  48                         val = ~val;
  49
  50                 if ((val & mask) == mask)
  51                         return 0;
  52
  53                 udelay(1);
  54         }
  55
  56         debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
  57               __func__, reg, mask, set);
  58
  59         return -ETIMEDOUT;
  60 }
  61
  62 /*
  63  * Initializes the FSLSPClkSel field of the HCFG register
  64  * depending on the PHY type.
  65  */
  66 static void init_fslspclksel(struct dwc2_core_regs *regs)
  67 {
  68         uint32_t phyclk;
  69
  70 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  71         phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  72 #else
  73         /* High speed PHY running at full speed or high speed */
  74         phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
  75 #endif
  76
  77 #ifdef CONFIG_DWC2_ULPI_FS_LS
  78         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  79         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  80                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  81         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
  82                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
  83
  84         if (hval == 2 && fval == 1)
  85                 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  86 #endif
  87
  88         clrsetbits_le32(&regs->host_regs.hcfg,
  89                         DWC2_HCFG_FSLSPCLKSEL_MASK,
  90                         phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
  91 }
  92
  93 /*
  94  * Flush a Tx FIFO.
  95  *
  96  * @param regs Programming view of DWC_otg controller.
  97  * @param num Tx FIFO to flush.
  98  */
  99 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
 100 {
 101         int ret;
 102
 103         writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
 104                &regs->grstctl);
 105         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
 106         if (ret)
 107                 printf("%s: Timeout!\n", __func__);
 108
 109         /* Wait for 3 PHY Clocks */
 110         udelay(1);
 111 }
 112
 113 /*
 114  * Flush Rx FIFO.
 115  *
 116  * @param regs Programming view of DWC_otg controller.
 117  */
 118 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
 119 {
 120         int ret;
 121
 122         writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
 123         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
 124         if (ret)
 125                 printf("%s: Timeout!\n", __func__);
 126
 127         /* Wait for 3 PHY Clocks */
 128         udelay(1);
 129 }
 130
 131 /*
 132  * Do core a soft reset of the core.  Be careful with this because it
 133  * resets all the internal state machines of the core.
 134  */
 135 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
 136 {
 137         int ret;
 138
 139         /* Wait for AHB master IDLE state. */
 140         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
 141         if (ret)
 142                 printf("%s: Timeout!\n", __func__);
 143
 144         /* Core Soft Reset */
 145         writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
 146         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_CSFTRST, 0);
 147         if (ret)
 148                 printf("%s: Timeout!\n", __func__);
 149
 150         /*
 151          * Wait for core to come out of reset.
 152          * NOTE: This long sleep is _very_ important, otherwise the core will
 153          *       not stay in host mode after a connector ID change!
 154          */
 155         mdelay(100);
 156 }
 157
 158 /*
 159  * This function initializes the DWC_otg controller registers for
 160  * host mode.
 161  *
 162  * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
 163  * request queues. Host channels are reset to ensure that they are ready for
 164  * performing transfers.
 165  *
 166  * @param regs Programming view of DWC_otg controller
 167  *
 168  */
 169 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
 170 {
 171         uint32_t nptxfifosize = 0;
 172         uint32_t ptxfifosize = 0;
 173         uint32_t hprt0 = 0;
 174         int i, ret, num_channels;
 175
 176         /* Restart the Phy Clock */
 177         writel(0, &regs->pcgcctl);
 178
 179         /* Initialize Host Configuration Register */
 180         init_fslspclksel(regs);
 181 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
 182         setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
 183 #endif
 184
 185         /* Configure data FIFO sizes */
 186 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
 187         if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
 188                 /* Rx FIFO */
 189                 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
 190
 191                 /* Non-periodic Tx FIFO */
 192                 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
 193                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 194                 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
 195                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 196                 writel(nptxfifosize, &regs->gnptxfsiz);
 197
 198                 /* Periodic Tx FIFO */
 199                 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
 200                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 201                 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
 202                                 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
 203                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 204                 writel(ptxfifosize, &regs->hptxfsiz);
 205         }
 206 #endif
 207
 208         /* Clear Host Set HNP Enable in the OTG Control Register */
 209         clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
 210
 211         /* Make sure the FIFOs are flushed. */
 212         dwc_otg_flush_tx_fifo(regs, 0x10);      /* All Tx FIFOs */
 213         dwc_otg_flush_rx_fifo(regs);
 214
 215         /* Flush out any leftover queued requests. */
 216         num_channels = readl(&regs->ghwcfg2);
 217         num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
 218         num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
 219         num_channels += 1;
 220
 221         for (i = 0; i < num_channels; i++)
 222                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 223                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
 224                                 DWC2_HCCHAR_CHDIS);
 225
 226         /* Halt all channels to put them into a known state. */
 227         for (i = 0; i < num_channels; i++) {
 228                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 229                                 DWC2_HCCHAR_EPDIR,
 230                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
 231                 ret = wait_for_bit(&regs->hc_regs[i].hcchar,
 232                                    DWC2_HCCHAR_CHEN, 0);
 233                 if (ret)
 234                         printf("%s: Timeout!\n", __func__);
 235         }
 236
 237         /* Turn on the vbus power. */
 238         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
 239                 hprt0 = readl(&regs->hprt0);
 240                 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
 241                 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
 242                 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
 243                         hprt0 |= DWC2_HPRT0_PRTPWR;
 244                         writel(hprt0, &regs->hprt0);
 245                 }
 246         }
 247 }
 248
 249 /*
 250  * This function initializes the DWC_otg controller registers and
 251  * prepares the core for device mode or host mode operation.
 252  *
 253  * @param regs Programming view of the DWC_otg controller
 254  */
 255 static void dwc_otg_core_init(struct dwc2_core_regs *regs)
 256 {
 257         uint32_t ahbcfg = 0;
 258         uint32_t usbcfg = 0;
 259         uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
 260
 261         /* Common Initialization */
 262         usbcfg = readl(&regs->gusbcfg);
 263
 264         /* Program the ULPI External VBUS bit if needed */
 265 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
 266         usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 267 #else
 268         usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 269 #endif
 270
 271         /* Set external TS Dline pulsing */
 272 #ifdef CONFIG_DWC2_TS_DLINE
 273         usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 274 #else
 275         usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 276 #endif
 277         writel(usbcfg, &regs->gusbcfg);
 278
 279         /* Reset the Controller */
 280         dwc_otg_core_reset(regs);
 281
 282         /*
 283          * This programming sequence needs to happen in FS mode before
 284          * any other programming occurs
 285          */
 286 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
 287         (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
 288         /* If FS mode with FS PHY */
 289         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
 290
 291         /* Reset after a PHY select */
 292         dwc_otg_core_reset(regs);
 293
 294         /*
 295          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
 296          * Also do this on HNP Dev/Host mode switches (done in dev_init
 297          * and host_init).
 298          */
 299         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
 300                 init_fslspclksel(regs);
 301
 302 #ifdef CONFIG_DWC2_I2C_ENABLE
 303         /* Program GUSBCFG.OtgUtmifsSel to I2C */
 304         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
 305
 306         /* Program GI2CCTL.I2CEn */
 307         clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
 308                         DWC2_GI2CCTL_I2CDEVADDR_MASK,
 309                         1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
 310         setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
 311 #endif
 312
 313 #else
 314         /* High speed PHY. */
 315
 316         /*
 317          * HS PHY parameters. These parameters are preserved during
 318          * soft reset so only program the first time. Do a soft reset
 319          * immediately after setting phyif.
 320          */
 321         usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
 322         usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
 323
 324         if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) {      /* ULPI interface */
 325 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
 326                 usbcfg |= DWC2_GUSBCFG_DDRSEL;
 327 #else
 328                 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
 329 #endif
 330         } else {        /* UTMI+ interface */
 331 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
 332                 usbcfg |= DWC2_GUSBCFG_PHYIF;
 333 #endif
 334         }
 335
 336         writel(usbcfg, &regs->gusbcfg);
 337
 338         /* Reset after setting the PHY parameters */
 339         dwc_otg_core_reset(regs);
 340 #endif
 341
 342         usbcfg = readl(&regs->gusbcfg);
 343         usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
 344 #ifdef CONFIG_DWC2_ULPI_FS_LS
 345         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
 346         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
 347                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
 348         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
 349                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
 350         if (hval == 2 && fval == 1) {
 351                 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
 352                 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
 353         }
 354 #endif
 355         writel(usbcfg, &regs->gusbcfg);
 356
 357         /* Program the GAHBCFG Register. */
 358         switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
 359         case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
 360                 break;
 361         case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
 362                 while (brst_sz > 1) {
 363                         ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
 364                         ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
 365                         brst_sz >>= 1;
 366                 }
 367
 368 #ifdef CONFIG_DWC2_DMA_ENABLE
 369                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 370 #endif
 371                 break;
 372
 373         case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
 374                 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
 375 #ifdef CONFIG_DWC2_DMA_ENABLE
 376                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 377 #endif
 378                 break;
 379         }
 380
 381         writel(ahbcfg, &regs->gahbcfg);
 382
 383         /* Program the GUSBCFG register for HNP/SRP. */
 384         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
 385
 386 #ifdef CONFIG_DWC2_IC_USB_CAP
 387         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
 388 #endif
 389 }
 390
 391 /*
 392  * Prepares a host channel for transferring packets to/from a specific
 393  * endpoint. The HCCHARn register is set up with the characteristics specified
 394  * in _hc. Host channel interrupts that may need to be serviced while this
 395  * transfer is in progress are enabled.
 396  *
 397  * @param regs Programming view of DWC_otg controller
 398  * @param hc Information needed to initialize the host channel
 399  */
 400 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
 401                 uint8_t dev_addr, uint8_t ep_num, uint8_t ep_is_in,
 402                 uint8_t ep_type, uint16_t max_packet)
 403 {
 404         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
 405         const uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
 406                                 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
 407                                 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
 408                                 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
 409                                 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
 410
 411         /* Clear old interrupt conditions for this host channel. */
 412         writel(0x3fff, &hc_regs->hcint);
 413
 414         /*
 415          * Program the HCCHARn register with the endpoint characteristics
 416          * for the current transfer.
 417          */
 418         writel(hcchar, &hc_regs->hcchar);
 419
 420         /* Program the HCSPLIT register for SPLITs */
 421         writel(0, &hc_regs->hcsplt);
 422 }
 423
 424 /*
 425  * DWC2 to USB API interface
 426  */
 427 /* Direction: In ; Request: Status */
 428 static int dwc_otg_submit_rh_msg_in_status(struct usb_device *dev, void *buffer,
 429                                            int txlen, struct devrequest *cmd)
 430 {
 431         uint32_t hprt0 = 0;
 432         uint32_t port_status = 0;
 433         uint32_t port_change = 0;
 434         int len = 0;
 435         int stat = 0;
 436
 437         switch (cmd->requesttype & ~USB_DIR_IN) {
 438         case 0:
 439                 *(uint16_t *)buffer = cpu_to_le16(1);
 440                 len = 2;
 441                 break;
 442         case USB_RECIP_INTERFACE:
 443         case USB_RECIP_ENDPOINT:
 444                 *(uint16_t *)buffer = cpu_to_le16(0);
 445                 len = 2;
 446                 break;
 447         case USB_TYPE_CLASS:
 448                 *(uint32_t *)buffer = cpu_to_le32(0);
 449                 len = 4;
 450                 break;
 451         case USB_RECIP_OTHER | USB_TYPE_CLASS:
 452                 hprt0 = readl(&regs->hprt0);
 453                 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
 454                         port_status |= USB_PORT_STAT_CONNECTION;
 455                 if (hprt0 & DWC2_HPRT0_PRTENA)
 456                         port_status |= USB_PORT_STAT_ENABLE;
 457                 if (hprt0 & DWC2_HPRT0_PRTSUSP)
 458                         port_status |= USB_PORT_STAT_SUSPEND;
 459                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
 460                         port_status |= USB_PORT_STAT_OVERCURRENT;
 461                 if (hprt0 & DWC2_HPRT0_PRTRST)
 462                         port_status |= USB_PORT_STAT_RESET;
 463                 if (hprt0 & DWC2_HPRT0_PRTPWR)
 464                         port_status |= USB_PORT_STAT_POWER;
 465
 466                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
 467                         port_status |= USB_PORT_STAT_LOW_SPEED;
 468                 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 469                          DWC2_HPRT0_PRTSPD_HIGH)
 470                         port_status |= USB_PORT_STAT_HIGH_SPEED;
 471
 472                 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
 473                         port_change |= USB_PORT_STAT_C_ENABLE;
 474                 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
 475                         port_change |= USB_PORT_STAT_C_CONNECTION;
 476                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
 477                         port_change |= USB_PORT_STAT_C_OVERCURRENT;
 478
 479                 *(uint32_t *)buffer = cpu_to_le32(port_status |
 480                                         (port_change << 16));
 481                 len = 4;
 482                 break;
 483         default:
 484                 puts("unsupported root hub command\n");
 485                 stat = USB_ST_STALLED;
 486         }
 487
 488         dev->act_len = min(len, txlen);
 489         dev->status = stat;
 490
 491         return stat;
 492 }
 493
 494 /* Direction: In ; Request: Descriptor */
 495 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
 496                                                void *buffer, int txlen,
 497                                                struct devrequest *cmd)
 498 {
 499         unsigned char data[32];
 500         uint32_t dsc;
 501         int len = 0;
 502         int stat = 0;
 503         uint16_t wValue = cpu_to_le16(cmd->value);
 504         uint16_t wLength = cpu_to_le16(cmd->length);
 505
 506         switch (cmd->requesttype & ~USB_DIR_IN) {
 507         case 0:
 508                 switch (wValue & 0xff00) {
 509                 case 0x0100:    /* device descriptor */
 510                         len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
 511                         memcpy(buffer, root_hub_dev_des, len);
 512                         break;
 513                 case 0x0200:    /* configuration descriptor */
 514                         len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
 515                         memcpy(buffer, root_hub_config_des, len);
 516                         break;
 517                 case 0x0300:    /* string descriptors */
 518                         switch (wValue & 0xff) {
 519                         case 0x00:
 520                                 len = min3(txlen, (int)sizeof(root_hub_str_index0),
 521                                            (int)wLength);
 522                                 memcpy(buffer, root_hub_str_index0, len);
 523                                 break;
 524                         case 0x01:
 525                                 len = min3(txlen, (int)sizeof(root_hub_str_index1),
 526                                            (int)wLength);
 527                                 memcpy(buffer, root_hub_str_index1, len);
 528                                 break;
 529                         }
 530                         break;
 531                 default:
 532                         stat = USB_ST_STALLED;
 533                 }
 534                 break;
 535
 536         case USB_TYPE_CLASS:
 537                 /* Root port config, set 1 port and nothing else. */
 538                 dsc = 0x00000001;
 539
 540                 data[0] = 9;            /* min length; */
 541                 data[1] = 0x29;
 542                 data[2] = dsc & RH_A_NDP;
 543                 data[3] = 0;
 544                 if (dsc & RH_A_PSM)
 545                         data[3] |= 0x1;
 546                 if (dsc & RH_A_NOCP)
 547                         data[3] |= 0x10;
 548                 else if (dsc & RH_A_OCPM)
 549                         data[3] |= 0x8;
 550
 551                 /* corresponds to data[4-7] */
 552                 data[5] = (dsc & RH_A_POTPGT) >> 24;
 553                 data[7] = dsc & RH_B_DR;
 554                 if (data[2] < 7) {
 555                         data[8] = 0xff;
 556                 } else {
 557                         data[0] += 2;
 558                         data[8] = (dsc & RH_B_DR) >> 8;
 559                         data[9] = 0xff;
 560                         data[10] = data[9];
 561                 }
 562
 563                 len = min3(txlen, (int)data[0], (int)wLength);
 564                 memcpy(buffer, data, len);
 565                 break;
 566         default:
 567                 puts("unsupported root hub command\n");
 568                 stat = USB_ST_STALLED;
 569         }
 570
 571         dev->act_len = min(len, txlen);
 572         dev->status = stat;
 573
 574         return stat;
 575 }
 576
 577 /* Direction: In ; Request: Configuration */
 578 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
 579                                                   void *buffer, int txlen,
 580                                                   struct devrequest *cmd)
 581 {
 582         int len = 0;
 583         int stat = 0;
 584
 585         switch (cmd->requesttype & ~USB_DIR_IN) {
 586         case 0:
 587                 *(uint8_t *)buffer = 0x01;
 588                 len = 1;
 589                 break;
 590         default:
 591                 puts("unsupported root hub command\n");
 592                 stat = USB_ST_STALLED;
 593         }
 594
 595         dev->act_len = min(len, txlen);
 596         dev->status = stat;
 597
 598         return stat;
 599 }
 600
 601 /* Direction: In */
 602 static int dwc_otg_submit_rh_msg_in(struct usb_device *dev,
 603                                  void *buffer, int txlen,
 604                                  struct devrequest *cmd)
 605 {
 606         switch (cmd->request) {
 607         case USB_REQ_GET_STATUS:
 608                 return dwc_otg_submit_rh_msg_in_status(dev, buffer,
 609                                                        txlen, cmd);
 610         case USB_REQ_GET_DESCRIPTOR:
 611                 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
 612                                                            txlen, cmd);
 613         case USB_REQ_GET_CONFIGURATION:
 614                 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
 615                                                               txlen, cmd);
 616         default:
 617                 puts("unsupported root hub command\n");
 618                 return USB_ST_STALLED;
 619         }
 620 }
 621
 622 /* Direction: Out */
 623 static int dwc_otg_submit_rh_msg_out(struct usb_device *dev,
 624                                  void *buffer, int txlen,
 625                                  struct devrequest *cmd)
 626 {
 627         int len = 0;
 628         int stat = 0;
 629         uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
 630         uint16_t wValue = cpu_to_le16(cmd->value);
 631
 632         switch (bmrtype_breq & ~USB_DIR_IN) {
 633         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
 634         case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
 635                 break;
 636
 637         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 638                 switch (wValue) {
 639                 case USB_PORT_FEAT_C_CONNECTION:
 640                         setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
 641                         break;
 642                 }
 643                 break;
 644
 645         case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 646                 switch (wValue) {
 647                 case USB_PORT_FEAT_SUSPEND:
 648                         break;
 649
 650                 case USB_PORT_FEAT_RESET:
 651                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 652                                         DWC2_HPRT0_PRTCONNDET |
 653                                         DWC2_HPRT0_PRTENCHNG |
 654                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 655                                         DWC2_HPRT0_PRTRST);
 656                         mdelay(50);
 657                         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
 658                         break;
 659
 660                 case USB_PORT_FEAT_POWER:
 661                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 662                                         DWC2_HPRT0_PRTCONNDET |
 663                                         DWC2_HPRT0_PRTENCHNG |
 664                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 665                                         DWC2_HPRT0_PRTRST);
 666                         break;
 667
 668                 case USB_PORT_FEAT_ENABLE:
 669                         break;
 670                 }
 671                 break;
 672         case (USB_REQ_SET_ADDRESS << 8):
 673                 root_hub_devnum = wValue;
 674                 break;
 675         case (USB_REQ_SET_CONFIGURATION << 8):
 676                 break;
 677         default:
 678                 puts("unsupported root hub command\n");
 679                 stat = USB_ST_STALLED;
 680         }
 681
 682         len = min(len, txlen);
 683
 684         dev->act_len = len;
 685         dev->status = stat;
 686
 687         return stat;
 688 }
 689
 690 static int dwc_otg_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
 691                                  void *buffer, int txlen,
 692                                  struct devrequest *cmd)
 693 {
 694         int stat = 0;
 695
 696         if (usb_pipeint(pipe)) {
 697                 puts("Root-Hub submit IRQ: NOT implemented\n");
 698                 return 0;
 699         }
 700
 701         if (cmd->requesttype & USB_DIR_IN)
 702                 stat = dwc_otg_submit_rh_msg_in(dev, buffer, txlen, cmd);
 703         else
 704                 stat = dwc_otg_submit_rh_msg_out(dev, buffer, txlen, cmd);
 705
 706         mdelay(1);
 707
 708         return stat;
 709 }
 710
 711 int wait_for_chhltd(uint32_t *sub, int *toggle, bool ignore_ack)
 712 {
 713         uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP | DWC2_HCINT_CHHLTD;
 714         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
 715         int ret;
 716         uint32_t hcint, hctsiz;
 717
 718         ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true);
 719         if (ret)
 720                 return ret;
 721
 722         hcint = readl(&hc_regs->hcint);
 723         if (ignore_ack)
 724                 hcint &= ~DWC2_HCINT_ACK;
 725         else
 726                 hcint_comp_hlt_ack |= DWC2_HCINT_ACK;
 727         if (hcint != hcint_comp_hlt_ack) {
 728                 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
 729                 return -EINVAL;
 730         }
 731
 732         hctsiz = readl(&hc_regs->hctsiz);
 733         *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
 734                 DWC2_HCTSIZ_XFERSIZE_OFFSET;
 735         *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
 736
 737         debug("%s: sub=%u toggle=%d\n", __func__, *sub, *toggle);
 738
 739         return 0;
 740 }
 741
 742 static int dwc2_eptype[] = {
 743         DWC2_HCCHAR_EPTYPE_ISOC,
 744         DWC2_HCCHAR_EPTYPE_INTR,
 745         DWC2_HCCHAR_EPTYPE_CONTROL,
 746         DWC2_HCCHAR_EPTYPE_BULK,
 747 };
 748
 749 int chunk_msg(struct usb_device *dev, unsigned long pipe, int *pid, int in,
 750               void *buffer, int len, bool ignore_ack)
 751 {
 752         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
 753         int devnum = usb_pipedevice(pipe);
 754         int ep = usb_pipeendpoint(pipe);
 755         int max = usb_maxpacket(dev, pipe);
 756         int eptype = dwc2_eptype[usb_pipetype(pipe)];
 757         int done = 0;
 758         int ret;
 759         uint32_t sub;
 760         uint32_t xfer_len;
 761         uint32_t num_packets;
 762         int stop_transfer = 0;
 763
 764         debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
 765               in, len);
 766
 767         do {
 768                 /* Initialize channel */
 769                 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, devnum, ep, in, eptype,
 770                                 max);
 771
 772                 xfer_len = len - done;
 773                 if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
 774                         xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1;
 775                 if (xfer_len > DWC2_DATA_BUF_SIZE)
 776                         xfer_len = DWC2_DATA_BUF_SIZE - max + 1;
 777
 778                 /* Make sure that xfer_len is a multiple of max packet size. */
 779                 if (xfer_len > 0) {
 780                         num_packets = (xfer_len + max - 1) / max;
 781                         if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) {
 782                                 num_packets = CONFIG_DWC2_MAX_PACKET_COUNT;
 783                                 xfer_len = num_packets * max;
 784                         }
 785                 } else {
 786                         num_packets = 1;
 787                 }
 788
 789                 if (in)
 790                         xfer_len = num_packets * max;
 791
 792                 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
 793                       *pid, xfer_len, num_packets);
 794
 795                 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
 796                        (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
 797                        (*pid << DWC2_HCTSIZ_PID_OFFSET),
 798                        &hc_regs->hctsiz);
 799
 800                 if (!in)
 801                         memcpy(aligned_buffer, (char *)buffer + done, len);
 802
 803                 writel(phys_to_bus((unsigned long)aligned_buffer),
 804                        &hc_regs->hcdma);
 805
 806                 /* Set host channel enable after all other setup is complete. */
 807                 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
 808                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
 809                                 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
 810                                 DWC2_HCCHAR_CHEN);
 811
 812                 ret = wait_for_chhltd(&sub, pid, ignore_ack);
 813                 if (ret) {
 814                         stop_transfer = 1;
 815                         break;
 816                 }
 817
 818                 if (in) {
 819                         xfer_len -= sub;
 820                         memcpy(buffer + done, aligned_buffer, xfer_len);
 821                         if (sub)
 822                                 stop_transfer = 1;
 823                 }
 824
 825                 done += xfer_len;
 826
 827         } while ((done < len) && !stop_transfer);
 828
 829         writel(0, &hc_regs->hcintmsk);
 830         writel(0xFFFFFFFF, &hc_regs->hcint);
 831
 832         dev->status = 0;
 833         dev->act_len = done;
 834
 835         return 0;
 836 }
 837
 838 /* U-Boot USB transmission interface */
 839 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 840                     int len)
 841 {
 842         int devnum = usb_pipedevice(pipe);
 843         int ep = usb_pipeendpoint(pipe);
 844
 845         if (devnum == root_hub_devnum) {
 846                 dev->status = 0;
 847                 return -EINVAL;
 848         }
 849
 850         return chunk_msg(dev, pipe, &bulk_data_toggle[devnum][ep],
 851                          usb_pipein(pipe), buffer, len, true);
 852 }
 853
 854 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 855                        int len, struct devrequest *setup)
 856 {
 857         int devnum = usb_pipedevice(pipe);
 858         int pid, ret, act_len;
 859         /* For CONTROL endpoint pid should start with DATA1 */
 860         int status_direction;
 861
 862         if (devnum == root_hub_devnum) {
 863                 dev->status = 0;
 864                 dev->speed = USB_SPEED_HIGH;
 865                 return dwc_otg_submit_rh_msg(dev, pipe, buffer, len, setup);
 866         }
 867
 868         pid = DWC2_HC_PID_SETUP;
 869         ret = chunk_msg(dev, pipe, &pid, 0, setup, 8, true);
 870         if (ret)
 871                 return ret;
 872
 873         if (buffer) {
 874                 pid = DWC2_HC_PID_DATA1;
 875                 ret = chunk_msg(dev, pipe, &pid, usb_pipein(pipe), buffer,
 876                                 len, false);
 877                 if (ret)
 878                         return ret;
 879                 act_len = dev->act_len;
 880         } /* End of DATA stage */
 881         else
 882                 act_len = 0;
 883
 884         /* STATUS stage */
 885         if ((len == 0) || usb_pipeout(pipe))
 886                 status_direction = 1;
 887         else
 888                 status_direction = 0;
 889
 890         pid = DWC2_HC_PID_DATA1;
 891         ret = chunk_msg(dev, pipe, &pid, status_direction, status_buffer, 0,
 892                 false);
 893         if (ret)
 894                 return ret;
 895
 896         dev->act_len = act_len;
 897
 898         return 0;
 899 }
 900
 901 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 902                    int len, int interval)
 903 {
 904         printf("dev = %p pipe = %#lx buf = %p size = %d int = %d\n",
 905                dev, pipe, buffer, len, interval);
 906         return -ENOSYS;
 907 }
 908
 909 /* U-Boot USB control interface */
 910 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 911 {
 912         uint32_t snpsid;
 913         int i, j;
 914
 915         root_hub_devnum = 0;
 916
 917         snpsid = readl(&regs->gsnpsid);
 918         printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
 919
 920         if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx) {
 921                 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
 922                 return -ENODEV;
 923         }
 924
 925         dwc_otg_core_init(regs);
 926         dwc_otg_core_host_init(regs);
 927
 928         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 929                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
 930                         DWC2_HPRT0_PRTOVRCURRCHNG,
 931                         DWC2_HPRT0_PRTRST);
 932         mdelay(50);
 933         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
 934                      DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
 935                      DWC2_HPRT0_PRTRST);
 936
 937         for (i = 0; i < MAX_DEVICE; i++) {
 938                 for (j = 0; j < MAX_ENDPOINT; j++)
 939                         bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
 940         }
 941
 942         return 0;
 943 }
 944
 945 int usb_lowlevel_stop(int index)
 946 {
 947         /* Put everything in reset. */
 948         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 949                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
 950                         DWC2_HPRT0_PRTOVRCURRCHNG,
 951                         DWC2_HPRT0_PRTRST);
 952         return 0;
 953 }