2 * SAMSUNG EXYNOS USB HOST EHCI Controller
4 * Copyright (C) 2012 Samsung Electronics Co.Ltd
5 * Vivek Gautam <gautam.vivek@samsung.com>
7 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/ehci.h>
17 #include <asm/arch/system.h>
18 #include <asm/arch/power.h>
19 #include <asm-generic/errno.h>
20 #include <linux/compat.h>
23 /* Declare global data pointer */
24 DECLARE_GLOBAL_DATA_PTR;
27 * Contains pointers to register base addresses
28 * for the usb controller.
31 struct exynos_usb_phy *usb;
32 struct ehci_hccr *hcd;
35 static struct exynos_ehci exynos;
37 #ifdef CONFIG_OF_CONTROL
38 static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
44 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_EHCI);
46 debug("EHCI: Can't get device node for ehci\n");
51 * Get the base address for EHCI controller from the device node
53 addr = fdtdec_get_addr(blob, node, "reg");
54 if (addr == FDT_ADDR_T_NONE) {
55 debug("Can't get the EHCI register address\n");
59 exynos->hcd = (struct ehci_hccr *)addr;
62 node = fdtdec_next_compatible_subnode(blob, node,
63 COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth);
65 debug("EHCI: Can't get device node for usb-phy controller\n");
70 * Get the base address for usbphy from the device node
72 exynos->usb = (struct exynos_usb_phy *)fdtdec_get_addr(blob, node,
74 if (exynos->usb == NULL) {
75 debug("Can't get the usbphy register address\n");
83 /* Setup the EHCI host controller. */
84 static void setup_usb_phy(struct exynos_usb_phy *usb)
86 set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
88 set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
90 clrbits_le32(&usb->usbphyctrl0,
91 HOST_CTRL0_FSEL_MASK |
92 HOST_CTRL0_COMMONON_N |
93 /* HOST Phy setting */
95 HOST_CTRL0_PHYSWRSTALL |
97 HOST_CTRL0_FORCESUSPEND |
98 HOST_CTRL0_FORCESLEEP);
100 setbits_le32(&usb->usbphyctrl0,
101 /* Setting up the ref freq */
103 /* HOST Phy setting */
104 HOST_CTRL0_LINKSWRST |
105 HOST_CTRL0_UTMISWRST);
107 clrbits_le32(&usb->usbphyctrl0,
108 HOST_CTRL0_LINKSWRST |
109 HOST_CTRL0_UTMISWRST);
112 /* EHCI Ctrl setting */
113 setbits_le32(&usb->ehcictrl,
114 EHCICTRL_ENAINCRXALIGN |
120 /* Reset the EHCI host controller. */
121 static void reset_usb_phy(struct exynos_usb_phy *usb)
124 setbits_le32(&usb->usbphyctrl0,
125 HOST_CTRL0_PHYSWRST |
126 HOST_CTRL0_PHYSWRSTALL |
128 HOST_CTRL0_FORCESUSPEND |
129 HOST_CTRL0_FORCESLEEP);
131 set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
135 * EHCI-initialization
136 * Create the appropriate control structures to manage
137 * a new EHCI host controller.
139 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
141 struct exynos_ehci *ctx = &exynos;
143 #ifdef CONFIG_OF_CONTROL
144 if (exynos_usb_parse_dt(gd->fdt_blob, ctx)) {
145 debug("Unable to parse device tree for ehci-exynos\n");
149 ctx->usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
150 ctx->hcd = (struct ehci_hccr *)samsung_get_base_usb_ehci();
153 setup_usb_phy(ctx->usb);
156 *hcor = (struct ehci_hcor *)((uint32_t) *hccr
157 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
159 debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
160 (uint32_t)*hccr, (uint32_t)*hcor,
161 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
167 * Destroy the appropriate control structures corresponding
168 * the EHCI host controller.
170 int ehci_hcd_stop(int index)
172 struct exynos_ehci *ctx = &exynos;
174 reset_usb_phy(ctx->usb);