2 * SAMSUNG EXYNOS USB HOST EHCI Controller
4 * Copyright (C) 2012 Samsung Electronics Co.Ltd
5 * Vivek Gautam <gautam.vivek@samsung.com>
7 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/ehci.h>
17 #include <asm/arch/system.h>
18 #include <asm/arch/power.h>
20 #include <asm-generic/errno.h>
21 #include <linux/compat.h>
24 /* Declare global data pointer */
25 DECLARE_GLOBAL_DATA_PTR;
28 * Contains pointers to register base addresses
29 * for the usb controller.
32 struct exynos_usb_phy *usb;
33 struct ehci_hccr *hcd;
34 struct fdt_gpio_state vbus_gpio;
37 static struct exynos_ehci exynos;
39 #ifdef CONFIG_OF_CONTROL
40 static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
46 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_EHCI);
48 debug("EHCI: Can't get device node for ehci\n");
53 * Get the base address for EHCI controller from the device node
55 addr = fdtdec_get_addr(blob, node, "reg");
56 if (addr == FDT_ADDR_T_NONE) {
57 debug("Can't get the EHCI register address\n");
61 exynos->hcd = (struct ehci_hccr *)addr;
64 fdtdec_decode_gpio(blob, node, "samsung,vbus-gpio", &exynos->vbus_gpio);
67 node = fdtdec_next_compatible_subnode(blob, node,
68 COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth);
70 debug("EHCI: Can't get device node for usb-phy controller\n");
75 * Get the base address for usbphy from the device node
77 exynos->usb = (struct exynos_usb_phy *)fdtdec_get_addr(blob, node,
79 if (exynos->usb == NULL) {
80 debug("Can't get the usbphy register address\n");
88 static void exynos5_setup_usb_phy(struct exynos_usb_phy *usb)
92 clrbits_le32(&usb->usbphyctrl0,
93 HOST_CTRL0_FSEL_MASK |
94 HOST_CTRL0_COMMONON_N |
95 /* HOST Phy setting */
97 HOST_CTRL0_PHYSWRSTALL |
99 HOST_CTRL0_FORCESUSPEND |
100 HOST_CTRL0_FORCESLEEP);
102 setbits_le32(&usb->usbphyctrl0,
103 /* Setting up the ref freq */
105 /* HOST Phy setting */
106 HOST_CTRL0_LINKSWRST |
107 HOST_CTRL0_UTMISWRST);
109 clrbits_le32(&usb->usbphyctrl0,
110 HOST_CTRL0_LINKSWRST |
111 HOST_CTRL0_UTMISWRST);
113 /* HSIC Phy Setting */
114 hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
115 HSIC_CTRL_FORCESLEEP |
118 clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
119 clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
121 hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK)
122 << HSIC_CTRL_REFCLKDIV_SHIFT)
123 | ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK)
124 << HSIC_CTRL_REFCLKSEL_SHIFT)
125 | HSIC_CTRL_UTMISWRST);
127 setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
128 setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
132 clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST |
133 HSIC_CTRL_UTMISWRST);
135 clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST |
136 HSIC_CTRL_UTMISWRST);
140 /* EHCI Ctrl setting */
141 setbits_le32(&usb->ehcictrl,
142 EHCICTRL_ENAINCRXALIGN |
148 static void exynos4412_setup_usb_phy(struct exynos4412_usb_phy *usb)
150 writel(CLK_24MHZ, &usb->usbphyclk);
152 clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
153 PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
154 PHYPWR_NORMAL_MASK_PHY0));
156 setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
158 clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
161 static void setup_usb_phy(struct exynos_usb_phy *usb)
163 set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
165 set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
167 if (cpu_is_exynos5())
168 exynos5_setup_usb_phy(usb);
169 else if (cpu_is_exynos4())
170 if (proid_is_exynos4412())
171 exynos4412_setup_usb_phy((struct exynos4412_usb_phy *)
175 static void exynos5_reset_usb_phy(struct exynos_usb_phy *usb)
180 setbits_le32(&usb->usbphyctrl0,
181 HOST_CTRL0_PHYSWRST |
182 HOST_CTRL0_PHYSWRSTALL |
184 HOST_CTRL0_FORCESUSPEND |
185 HOST_CTRL0_FORCESLEEP);
188 hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
189 HSIC_CTRL_FORCESLEEP |
193 setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
194 setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
197 static void exynos4412_reset_usb_phy(struct exynos4412_usb_phy *usb)
199 setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
200 PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
201 PHYPWR_NORMAL_MASK_PHY0));
204 /* Reset the EHCI host controller. */
205 static void reset_usb_phy(struct exynos_usb_phy *usb)
207 if (cpu_is_exynos5())
208 exynos5_reset_usb_phy(usb);
209 else if (cpu_is_exynos4())
210 if (proid_is_exynos4412())
211 exynos4412_reset_usb_phy((struct exynos4412_usb_phy *)
214 set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
218 * EHCI-initialization
219 * Create the appropriate control structures to manage
220 * a new EHCI host controller.
222 int ehci_hcd_init(int index, enum usb_init_type init,
223 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
225 struct exynos_ehci *ctx = &exynos;
227 #ifdef CONFIG_OF_CONTROL
228 if (exynos_usb_parse_dt(gd->fdt_blob, ctx)) {
229 debug("Unable to parse device tree for ehci-exynos\n");
233 ctx->usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
234 ctx->hcd = (struct ehci_hccr *)samsung_get_base_usb_ehci();
237 #ifdef CONFIG_OF_CONTROL
238 /* setup the Vbus gpio here */
239 if (fdt_gpio_isvalid(&ctx->vbus_gpio) &&
240 !fdtdec_setup_gpio(&ctx->vbus_gpio))
241 gpio_direction_output(ctx->vbus_gpio.gpio, 1);
244 setup_usb_phy(ctx->usb);
246 board_usb_init(index, init);
249 *hcor = (struct ehci_hcor *)((uint32_t) *hccr
250 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
252 debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
253 (uint32_t)*hccr, (uint32_t)*hcor,
254 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
260 * Destroy the appropriate control structures corresponding
261 * the EHCI host controller.
263 int ehci_hcd_stop(int index)
265 struct exynos_ehci *ctx = &exynos;
267 reset_usb_phy(ctx->usb);