2 * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
6 * Author: Tor Krill tor@excito.com
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <usb/ehci-fsl.h>
17 #include <asm/fsl_errata.h>
21 /* Check USB PHY clock valid */
22 static int usb_phy_clk_valid(struct usb_ehci *ehci)
24 if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
25 in_be32(&ehci->prictrl))) {
26 printf("USB PHY clock invalid!\n");
34 * Create the appropriate control structures to manage
35 * a new EHCI host controller.
37 * Excerpts from linux ehci fsl driver.
39 int ehci_hcd_init(int index, enum usb_init_type init,
40 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
42 struct usb_ehci *ehci = NULL;
43 const char *phy_type = NULL;
45 char current_usb_controller[5];
46 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
51 if (has_erratum_a007075()) {
53 * A 5ms delay is needed after applying soft-reset to the
54 * controller to let external ULPI phy come out of reset.
55 * This delay needs to be added before re-initializing
56 * the controller after soft-resetting completes
60 memset(current_usb_controller, '\0', 5);
61 snprintf(current_usb_controller, 4, "usb%d", index+1);
65 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
68 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
71 printf("ERROR: wrong controller index!!\n");
75 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
76 *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
77 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
79 /* Set to Host mode */
80 setbits_le32(&ehci->usbmode, CM_HOST);
82 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
83 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
86 if (hwconfig_sub(current_usb_controller, "phy_type"))
87 phy_type = hwconfig_subarg(current_usb_controller,
90 phy_type = getenv("usb_phy_type");
93 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
94 /* if none specified assume internal UTMI */
95 strcpy(usb_phy, "utmi");
98 printf("WARNING: USB phy type not defined !!\n");
103 if (!strncmp(phy_type, "utmi", 4)) {
104 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
105 setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
106 setbits_be32(&ehci->control, UTMI_PHY_EN);
107 udelay(1000); /* delay required for PHY Clk to appear */
109 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
110 setbits_be32(&ehci->control, USB_EN);
112 setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
113 clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
114 udelay(1000); /* delay required for PHY Clk to appear */
115 if (!usb_phy_clk_valid(ehci))
117 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
120 out_be32(&ehci->prictrl, 0x0000000c);
121 out_be32(&ehci->age_cnt_limit, 0x00000040);
122 out_be32(&ehci->sictrl, 0x00000001);
124 in_le32(&ehci->usbmode);
130 * Destroy the appropriate control structures corresponding
131 * the the EHCI host controller.
133 int ehci_hcd_stop(int index)