2 * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
6 * Author: Tor Krill tor@excito.com
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <usb/ehci-fsl.h>
20 /* Check USB PHY clock valid */
21 static int usb_phy_clk_valid(struct usb_ehci *ehci)
23 if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
24 in_be32(&ehci->prictrl))) {
25 printf("USB PHY clock invalid!\n");
33 * Create the appropriate control structures to manage
34 * a new EHCI host controller.
36 * Excerpts from linux ehci fsl driver.
38 int ehci_hcd_init(int index, enum usb_init_type init,
39 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
41 struct usb_ehci *ehci = NULL;
42 const char *phy_type = NULL;
44 char current_usb_controller[5];
45 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
50 memset(current_usb_controller, '\0', 5);
51 snprintf(current_usb_controller, 4, "usb%d", index+1);
55 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
58 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
61 printf("ERROR: wrong controller index!!\n");
65 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
66 *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
67 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
69 /* Set to Host mode */
70 setbits_le32(&ehci->usbmode, CM_HOST);
72 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
73 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
76 if (hwconfig_sub(current_usb_controller, "phy_type"))
77 phy_type = hwconfig_subarg(current_usb_controller,
80 phy_type = getenv("usb_phy_type");
83 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
84 /* if none specified assume internal UTMI */
85 strcpy(usb_phy, "utmi");
88 printf("WARNING: USB phy type not defined !!\n");
93 if (!strncmp(phy_type, "utmi", 4)) {
94 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
95 setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
96 setbits_be32(&ehci->control, UTMI_PHY_EN);
97 udelay(1000); /* delay required for PHY Clk to appear */
99 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
100 setbits_be32(&ehci->control, USB_EN);
102 setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
103 clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
104 udelay(1000); /* delay required for PHY Clk to appear */
105 if (!usb_phy_clk_valid(ehci))
107 out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
110 out_be32(&ehci->prictrl, 0x0000000c);
111 out_be32(&ehci->age_cnt_limit, 0x00000040);
112 out_be32(&ehci->sictrl, 0x00000001);
114 in_le32(&ehci->usbmode);
120 * Destroy the appropriate control structures corresponding
121 * the the EHCI host controller.
123 int ehci_hcd_stop(int index)