2 * Copyright (c) 2007-2008, Juniper Networks, Inc.
3 * Copyright (c) 2008, Excito Elektronik i Skåne AB
4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2 of
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/byteorder.h>
26 #include <asm/unaligned.h>
31 #include <linux/compiler.h>
35 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
36 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
39 static struct ehci_ctrl {
40 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
41 struct ehci_hcor *hcor;
44 struct QH qh_list __aligned(USB_DMA_MINALIGN);
45 struct QH periodic_queue __aligned(USB_DMA_MINALIGN);
46 uint32_t *periodic_list;
48 } ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
50 #define ALIGN_END_ADDR(type, ptr, size) \
51 ((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
53 static struct descriptor {
54 struct usb_hub_descriptor hub;
55 struct usb_device_descriptor device;
56 struct usb_linux_config_descriptor config;
57 struct usb_linux_interface_descriptor interface;
58 struct usb_endpoint_descriptor endpoint;
59 } __attribute__ ((packed)) descriptor = {
61 0x8, /* bDescLength */
62 0x29, /* bDescriptorType: hub descriptor */
63 2, /* bNrPorts -- runtime modified */
64 0, /* wHubCharacteristics */
65 10, /* bPwrOn2PwrGood */
66 0, /* bHubCntrCurrent */
67 {}, /* Device removable */
68 {} /* at most 7 ports! XXX */
72 1, /* bDescriptorType: UDESC_DEVICE */
73 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
74 9, /* bDeviceClass: UDCLASS_HUB */
75 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
76 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
77 64, /* bMaxPacketSize: 64 bytes */
78 0x0000, /* idVendor */
79 0x0000, /* idProduct */
80 cpu_to_le16(0x0100), /* bcdDevice */
81 1, /* iManufacturer */
83 0, /* iSerialNumber */
84 1 /* bNumConfigurations: 1 */
88 2, /* bDescriptorType: UDESC_CONFIG */
90 1, /* bNumInterface */
91 1, /* bConfigurationValue */
92 0, /* iConfiguration */
93 0x40, /* bmAttributes: UC_SELF_POWER */
98 4, /* bDescriptorType: UDESC_INTERFACE */
99 0, /* bInterfaceNumber */
100 0, /* bAlternateSetting */
101 1, /* bNumEndpoints */
102 9, /* bInterfaceClass: UICLASS_HUB */
103 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
104 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
109 5, /* bDescriptorType: UDESC_ENDPOINT */
110 0x81, /* bEndpointAddress:
111 * UE_DIR_IN | EHCI_INTR_ENDPT
113 3, /* bmAttributes: UE_INTERRUPT */
114 8, /* wMaxPacketSize */
119 #if defined(CONFIG_EHCI_IS_TDI)
120 #define ehci_is_TDI() (1)
122 #define ehci_is_TDI() (0)
125 int __ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
127 return PORTSC_PSPD(reg);
130 int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
131 __attribute__((weak, alias("__ehci_get_port_speed")));
133 void __ehci_set_usbmode(int index)
138 reg_ptr = (uint32_t *)((u8 *)&ehcic[index].hcor->or_usbcmd + USBMODE);
139 tmp = ehci_readl(reg_ptr);
140 tmp |= USBMODE_CM_HC;
141 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
144 ehci_writel(reg_ptr, tmp);
147 void ehci_set_usbmode(int index)
148 __attribute__((weak, alias("__ehci_set_usbmode")));
150 void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
155 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
156 __attribute__((weak, alias("__ehci_powerup_fixup")));
158 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
162 result = ehci_readl(ptr);
164 if (result == ~(uint32_t)0)
174 static int ehci_reset(int index)
179 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
180 cmd = (cmd & ~CMD_RUN) | CMD_RESET;
181 ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
182 ret = handshake((uint32_t *)&ehcic[index].hcor->or_usbcmd,
183 CMD_RESET, 0, 250 * 1000);
185 printf("EHCI fail to reset\n");
190 ehci_set_usbmode(index);
192 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
193 cmd = ehci_readl(&ehcic[index].hcor->or_txfilltuning);
194 cmd &= ~TXFIFO_THRESH_MASK;
195 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
196 ehci_writel(&ehcic[index].hcor->or_txfilltuning, cmd);
202 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
204 uint32_t delta, next;
205 uint32_t addr = (uint32_t)buf;
208 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
209 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
211 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
214 while (idx < QT_BUFFER_CNT) {
215 td->qt_buffer[idx] = cpu_to_hc32(addr);
216 td->qt_buffer_hi[idx] = 0;
217 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
226 if (idx == QT_BUFFER_CNT) {
227 printf("out of buffer pointers (%u bytes left)\n", sz);
234 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
236 #define QH_HIGH_SPEED 2
237 #define QH_FULL_SPEED 0
238 #define QH_LOW_SPEED 1
239 if (speed == USB_SPEED_HIGH)
240 return QH_HIGH_SPEED;
241 if (speed == USB_SPEED_LOW)
243 return QH_FULL_SPEED;
247 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
248 int length, struct devrequest *req)
250 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
254 volatile struct qTD *vtd;
257 uint32_t endpt, maxpacket, token, usbsts;
262 struct ehci_ctrl *ctrl = dev->controller;
264 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
265 buffer, length, req);
267 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
268 req->request, req->request,
269 req->requesttype, req->requesttype,
270 le16_to_cpu(req->value), le16_to_cpu(req->value),
271 le16_to_cpu(req->index));
273 #define PKT_ALIGN 512
275 * The USB transfer is split into qTD transfers. Eeach qTD transfer is
276 * described by a transfer descriptor (the qTD). The qTDs form a linked
277 * list with a queue head (QH).
279 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
280 * have its beginning in a qTD transfer and its end in the following
281 * one, so the qTD transfer lengths have to be chosen accordingly.
283 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
284 * single pages. The first data buffer can start at any offset within a
285 * page (not considering the cache-line alignment issues), while the
286 * following buffers must be page-aligned. There is no alignment
287 * constraint on the size of a qTD transfer.
290 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
292 if (length > 0 || req == NULL) {
294 * Determine the qTD transfer size that will be used for the
295 * data payload (not considering the first qTD transfer, which
296 * may be longer or shorter, and the final one, which may be
299 * In order to keep each packet within a qTD transfer, the qTD
300 * transfer size is aligned to PKT_ALIGN, which is a multiple of
301 * wMaxPacketSize (except in some cases for interrupt transfers,
302 * see comment in submit_int_msg()).
304 * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
305 * QT_BUFFER_CNT full pages will be used.
307 int xfr_sz = QT_BUFFER_CNT;
309 * However, if the input buffer is not aligned to PKT_ALIGN, the
310 * qTD transfer size will be one page shorter, and the first qTD
311 * data buffer of each transfer will be page-unaligned.
313 if ((uint32_t)buffer & (PKT_ALIGN - 1))
315 /* Convert the qTD transfer size to bytes. */
316 xfr_sz *= EHCI_PAGE_SIZE;
318 * Approximate by excess the number of qTDs that will be
319 * required for the data payload. The exact formula is way more
320 * complicated and saves at most 2 qTDs, i.e. a total of 128
323 qtd_count += 2 + length / xfr_sz;
326 * Threshold value based on the worst-case total size of the allocated qTDs for
327 * a mass-storage transfer of 65535 blocks of 512 bytes.
329 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
330 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
332 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
334 printf("unable to allocate TDs\n");
338 memset(qh, 0, sizeof(struct QH));
339 memset(qtd, 0, qtd_count * sizeof(*qtd));
341 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
344 * Setup QH (3.6 in ehci-r10.pdf)
346 * qh_link ................. 03-00 H
347 * qh_endpt1 ............... 07-04 H
348 * qh_endpt2 ............... 0B-08 H
350 * qh_overlay.qt_next ...... 13-10 H
351 * - qh_overlay.qt_altnext
353 qh->qh_link = cpu_to_hc32((uint32_t)&ctrl->qh_list | QH_LINK_TYPE_QH);
354 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
355 maxpacket = usb_maxpacket(dev, pipe);
356 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
357 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
358 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
359 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
360 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
361 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
362 qh->qh_endpt1 = cpu_to_hc32(endpt);
363 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_PORTNUM(dev->portnr) |
364 QH_ENDPT2_HUBADDR(dev->parent->devnum) |
365 QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
366 qh->qh_endpt2 = cpu_to_hc32(endpt);
367 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
369 tdp = &qh->qh_overlay.qt_next;
373 * Setup request qTD (3.5 in ehci-r10.pdf)
375 * qt_next ................ 03-00 H
376 * qt_altnext ............. 07-04 H
377 * qt_token ............... 0B-08 H
379 * [ buffer, buffer_hi ] loaded with "req".
381 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
382 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
383 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
384 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
385 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
386 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
387 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
388 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
389 printf("unable to construct SETUP TD\n");
392 /* Update previous qTD! */
393 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
394 tdp = &qtd[qtd_counter++].qt_next;
398 if (length > 0 || req == NULL) {
399 uint8_t *buf_ptr = buffer;
400 int left_length = length;
404 * Determine the size of this qTD transfer. By default,
405 * QT_BUFFER_CNT full pages can be used.
407 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
409 * However, if the input buffer is not page-aligned, the
410 * portion of the first page before the buffer start
411 * offset within that page is unusable.
413 xfr_bytes -= (uint32_t)buf_ptr & (EHCI_PAGE_SIZE - 1);
415 * In order to keep each packet within a qTD transfer,
416 * align the qTD transfer size to PKT_ALIGN.
418 xfr_bytes &= ~(PKT_ALIGN - 1);
420 * This transfer may be shorter than the available qTD
421 * transfer size that has just been computed.
423 xfr_bytes = min(xfr_bytes, left_length);
426 * Setup request qTD (3.5 in ehci-r10.pdf)
428 * qt_next ................ 03-00 H
429 * qt_altnext ............. 07-04 H
430 * qt_token ............... 0B-08 H
432 * [ buffer, buffer_hi ] loaded with "buffer".
434 qtd[qtd_counter].qt_next =
435 cpu_to_hc32(QT_NEXT_TERMINATE);
436 qtd[qtd_counter].qt_altnext =
437 cpu_to_hc32(QT_NEXT_TERMINATE);
438 token = QT_TOKEN_DT(toggle) |
439 QT_TOKEN_TOTALBYTES(xfr_bytes) |
440 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
442 QT_TOKEN_PID(usb_pipein(pipe) ?
443 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
444 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
445 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
446 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
448 printf("unable to construct DATA TD\n");
451 /* Update previous qTD! */
452 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
453 tdp = &qtd[qtd_counter++].qt_next;
455 * Data toggle has to be adjusted since the qTD transfer
456 * size is not always an even multiple of
459 if ((xfr_bytes / maxpacket) & 1)
461 buf_ptr += xfr_bytes;
462 left_length -= xfr_bytes;
463 } while (left_length > 0);
468 * Setup request qTD (3.5 in ehci-r10.pdf)
470 * qt_next ................ 03-00 H
471 * qt_altnext ............. 07-04 H
472 * qt_token ............... 0B-08 H
474 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
475 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
476 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
477 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
478 QT_TOKEN_PID(usb_pipein(pipe) ?
479 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
480 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
481 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
482 /* Update previous qTD! */
483 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
484 tdp = &qtd[qtd_counter++].qt_next;
487 ctrl->qh_list.qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH);
490 flush_dcache_range((uint32_t)&ctrl->qh_list,
491 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
492 flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1));
493 flush_dcache_range((uint32_t)qtd,
494 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
496 /* Set async. queue head pointer. */
497 ehci_writel(&ctrl->hcor->or_asynclistaddr, (uint32_t)&ctrl->qh_list);
499 usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
500 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
502 /* Enable async. schedule. */
503 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
505 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
507 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
510 printf("EHCI fail timeout STS_ASS set\n");
514 /* Wait for TDs to be processed. */
516 vtd = &qtd[qtd_counter - 1];
517 timeout = USB_TIMEOUT_MS(pipe);
519 /* Invalidate dcache */
520 invalidate_dcache_range((uint32_t)&ctrl->qh_list,
521 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
522 invalidate_dcache_range((uint32_t)qh,
523 ALIGN_END_ADDR(struct QH, qh, 1));
524 invalidate_dcache_range((uint32_t)qtd,
525 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
527 token = hc32_to_cpu(vtd->qt_token);
528 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
531 } while (get_timer(ts) < timeout);
534 * Invalidate the memory area occupied by buffer
535 * Don't try to fix the buffer alignment, if it isn't properly
536 * aligned it's upper layer's fault so let invalidate_dcache_range()
537 * vow about it. But we have to fix the length as it's actual
538 * transfer length and can be unaligned. This is potentially
539 * dangerous operation, it's responsibility of the calling
540 * code to make sure enough space is reserved.
542 invalidate_dcache_range((uint32_t)buffer,
543 ALIGN((uint32_t)buffer + length, ARCH_DMA_MINALIGN));
545 /* Check that the TD processing happened */
546 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
547 printf("EHCI timed out on TD - token=%#x\n", token);
549 /* Disable async schedule. */
550 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
552 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
554 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
557 printf("EHCI fail timeout STS_ASS reset\n");
561 token = hc32_to_cpu(qh->qh_overlay.qt_token);
562 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
563 debug("TOKEN=%#x\n", token);
564 switch (QT_TOKEN_GET_STATUS(token) &
565 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
567 toggle = QT_TOKEN_GET_DT(token);
568 usb_settoggle(dev, usb_pipeendpoint(pipe),
569 usb_pipeout(pipe), toggle);
572 case QT_TOKEN_STATUS_HALTED:
573 dev->status = USB_ST_STALLED;
575 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
576 case QT_TOKEN_STATUS_DATBUFERR:
577 dev->status = USB_ST_BUF_ERR;
579 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
580 case QT_TOKEN_STATUS_BABBLEDET:
581 dev->status = USB_ST_BABBLE_DET;
584 dev->status = USB_ST_CRC_ERR;
585 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
586 dev->status |= USB_ST_STALLED;
589 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
592 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
593 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
594 ehci_readl(&ctrl->hcor->or_portsc[0]),
595 ehci_readl(&ctrl->hcor->or_portsc[1]));
599 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
607 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
608 int length, struct devrequest *req)
615 uint32_t *status_reg;
616 int port = le16_to_cpu(req->index) & 0xff;
617 struct ehci_ctrl *ctrl = dev->controller;
619 if (port > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
620 printf("The request port(%d) is not configured\n", port - 1);
623 status_reg = (uint32_t *)&ctrl->hcor->or_portsc[port - 1];
626 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
627 req->request, req->request,
628 req->requesttype, req->requesttype,
629 le16_to_cpu(req->value), le16_to_cpu(req->index));
631 typeReq = req->request | req->requesttype << 8;
634 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
635 switch (le16_to_cpu(req->value) >> 8) {
637 debug("USB_DT_DEVICE request\n");
638 srcptr = &descriptor.device;
639 srclen = descriptor.device.bLength;
642 debug("USB_DT_CONFIG config\n");
643 srcptr = &descriptor.config;
644 srclen = descriptor.config.bLength +
645 descriptor.interface.bLength +
646 descriptor.endpoint.bLength;
649 debug("USB_DT_STRING config\n");
650 switch (le16_to_cpu(req->value) & 0xff) {
651 case 0: /* Language */
656 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
659 case 2: /* Product */
660 srcptr = "\52\3E\0H\0C\0I\0 "
662 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
666 debug("unknown value DT_STRING %x\n",
667 le16_to_cpu(req->value));
672 debug("unknown value %x\n", le16_to_cpu(req->value));
676 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
677 switch (le16_to_cpu(req->value) >> 8) {
679 debug("USB_DT_HUB config\n");
680 srcptr = &descriptor.hub;
681 srclen = descriptor.hub.bLength;
684 debug("unknown value %x\n", le16_to_cpu(req->value));
688 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
689 debug("USB_REQ_SET_ADDRESS\n");
690 ctrl->rootdev = le16_to_cpu(req->value);
692 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
693 debug("USB_REQ_SET_CONFIGURATION\n");
696 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
697 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
702 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
703 memset(tmpbuf, 0, 4);
704 reg = ehci_readl(status_reg);
705 if (reg & EHCI_PS_CS)
706 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
707 if (reg & EHCI_PS_PE)
708 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
709 if (reg & EHCI_PS_SUSP)
710 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
711 if (reg & EHCI_PS_OCA)
712 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
713 if (reg & EHCI_PS_PR)
714 tmpbuf[0] |= USB_PORT_STAT_RESET;
715 if (reg & EHCI_PS_PP)
716 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
719 switch (ehci_get_port_speed(ctrl->hcor, reg)) {
723 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
727 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
731 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
734 if (reg & EHCI_PS_CSC)
735 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
736 if (reg & EHCI_PS_PEC)
737 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
738 if (reg & EHCI_PS_OCC)
739 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
740 if (ctrl->portreset & (1 << port))
741 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
746 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
747 reg = ehci_readl(status_reg);
748 reg &= ~EHCI_PS_CLEAR;
749 switch (le16_to_cpu(req->value)) {
750 case USB_PORT_FEAT_ENABLE:
752 ehci_writel(status_reg, reg);
754 case USB_PORT_FEAT_POWER:
755 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
757 ehci_writel(status_reg, reg);
760 case USB_PORT_FEAT_RESET:
761 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
763 EHCI_PS_IS_LOWSPEED(reg)) {
764 /* Low speed device, give up ownership. */
765 debug("port %d low speed --> companion\n",
768 ehci_writel(status_reg, reg);
775 ehci_writel(status_reg, reg);
777 * caller must wait, then call GetPortStatus
778 * usb 2.0 specification say 50 ms resets on
781 ehci_powerup_fixup(status_reg, ®);
783 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
785 * A host controller must terminate the reset
786 * and stabilize the state of the port within
789 ret = handshake(status_reg, EHCI_PS_PR, 0,
792 ctrl->portreset |= 1 << port;
794 printf("port(%d) reset error\n",
798 case USB_PORT_FEAT_TEST:
800 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
801 ehci_writel(status_reg, reg);
804 debug("unknown feature %x\n", le16_to_cpu(req->value));
807 /* unblock posted writes */
808 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
810 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
811 reg = ehci_readl(status_reg);
812 switch (le16_to_cpu(req->value)) {
813 case USB_PORT_FEAT_ENABLE:
816 case USB_PORT_FEAT_C_ENABLE:
817 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
819 case USB_PORT_FEAT_POWER:
820 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
821 reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
822 case USB_PORT_FEAT_C_CONNECTION:
823 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
825 case USB_PORT_FEAT_OVER_CURRENT:
826 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
828 case USB_PORT_FEAT_C_RESET:
829 ctrl->portreset &= ~(1 << port);
832 debug("unknown feature %x\n", le16_to_cpu(req->value));
835 ehci_writel(status_reg, reg);
836 /* unblock posted write */
837 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
840 debug("Unknown request\n");
845 len = min3(srclen, le16_to_cpu(req->length), length);
846 if (srcptr != NULL && len > 0)
847 memcpy(buffer, srcptr, len);
856 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
857 req->requesttype, req->request, le16_to_cpu(req->value),
858 le16_to_cpu(req->index), le16_to_cpu(req->length));
861 dev->status = USB_ST_STALLED;
865 int usb_lowlevel_stop(int index)
867 return ehci_hcd_stop(index);
870 int usb_lowlevel_init(int index, void **controller)
878 if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor))
881 /* EHCI spec section 4.1 */
882 if (ehci_reset(index))
885 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
886 if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor))
889 /* Set the high address word (aka segment) for 64-bit controller */
890 if (ehci_readl(&ehcic[index].hccr->cr_hccparams) & 1)
891 ehci_writel(ehcic[index].hcor->or_ctrldssegment, 0);
893 qh_list = &ehcic[index].qh_list;
895 /* Set head of reclaim list */
896 memset(qh_list, 0, sizeof(*qh_list));
897 qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
898 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
899 QH_ENDPT1_EPS(USB_SPEED_HIGH));
900 qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
901 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
902 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
903 qh_list->qh_overlay.qt_token =
904 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
906 /* Set async. queue head pointer. */
907 ehci_writel(&ehcic[index].hcor->or_asynclistaddr, (uint32_t)qh_list);
910 * Set up periodic list
911 * Step 1: Parent QH for all periodic transfers.
913 periodic = &ehcic[index].periodic_queue;
914 memset(periodic, 0, sizeof(*periodic));
915 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
916 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
917 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
920 * Step 2: Setup frame-list: Every microframe, USB tries the same list.
921 * In particular, device specifications on polling frequency
922 * are disregarded. Keyboards seem to send NAK/NYet reliably
923 * when polled with an empty buffer.
925 * Split Transactions will be spread across microframes using
928 ehcic[index].periodic_list = memalign(4096, 1024*4);
929 if (!ehcic[index].periodic_list)
931 for (i = 0; i < 1024; i++) {
932 ehcic[index].periodic_list[i] = (uint32_t)periodic
936 /* Set periodic list base address */
937 ehci_writel(&ehcic[index].hcor->or_periodiclistbase,
938 (uint32_t)ehcic[index].periodic_list);
940 reg = ehci_readl(&ehcic[index].hccr->cr_hcsparams);
941 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
942 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
943 /* Port Indicators */
944 if (HCS_INDICATOR(reg))
945 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
946 | 0x80, &descriptor.hub.wHubCharacteristics);
947 /* Port Power Control */
949 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
950 | 0x01, &descriptor.hub.wHubCharacteristics);
952 /* Start the host controller. */
953 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
955 * Philips, Intel, and maybe others need CMD_RUN before the
956 * root hub will detect new devices (why?); NEC doesn't
958 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
960 ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
962 /* take control over the ports */
963 cmd = ehci_readl(&ehcic[index].hcor->or_configflag);
965 ehci_writel(&ehcic[index].hcor->or_configflag, cmd);
966 /* unblock posted write */
967 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
969 reg = HC_VERSION(ehci_readl(&ehcic[index].hccr->cr_capbase));
970 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
972 ehcic[index].rootdev = 0;
974 *controller = &ehcic[index];
979 submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
983 if (usb_pipetype(pipe) != PIPE_BULK) {
984 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
987 return ehci_submit_async(dev, pipe, buffer, length, NULL);
991 submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
992 int length, struct devrequest *setup)
994 struct ehci_ctrl *ctrl = dev->controller;
996 if (usb_pipetype(pipe) != PIPE_CONTROL) {
997 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
1001 if (usb_pipedevice(pipe) == ctrl->rootdev) {
1003 dev->speed = USB_SPEED_HIGH;
1004 return ehci_submit_root(dev, pipe, buffer, length, setup);
1006 return ehci_submit_async(dev, pipe, buffer, length, setup);
1016 #define NEXT_QH(qh) (struct QH *)((qh)->qh_link & ~0x1f)
1019 enable_periodic(struct ehci_ctrl *ctrl)
1022 struct ehci_hcor *hcor = ctrl->hcor;
1025 cmd = ehci_readl(&hcor->or_usbcmd);
1027 ehci_writel(&hcor->or_usbcmd, cmd);
1029 ret = handshake((uint32_t *)&hcor->or_usbsts,
1030 STS_PSS, STS_PSS, 100 * 1000);
1032 printf("EHCI failed: timeout when enabling periodic list\n");
1040 disable_periodic(struct ehci_ctrl *ctrl)
1043 struct ehci_hcor *hcor = ctrl->hcor;
1046 cmd = ehci_readl(&hcor->or_usbcmd);
1048 ehci_writel(&hcor->or_usbcmd, cmd);
1050 ret = handshake((uint32_t *)&hcor->or_usbsts,
1051 STS_PSS, 0, 100 * 1000);
1053 printf("EHCI failed: timeout when disabling periodic list\n");
1059 static int periodic_schedules;
1062 create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize,
1063 int elementsize, void *buffer)
1065 struct ehci_ctrl *ctrl = dev->controller;
1066 struct int_queue *result = NULL;
1069 debug("Enter create_int_queue\n");
1070 if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1071 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1075 /* limit to 4 full pages worth of data -
1076 * we can safely fit them in a single TD,
1077 * no matter the alignment
1079 if (elementsize >= 16384) {
1080 debug("too large elements for interrupt transfers\n");
1084 result = malloc(sizeof(*result));
1086 debug("ehci intr queue: out of memory\n");
1089 result->first = memalign(32, sizeof(struct QH) * queuesize);
1090 if (!result->first) {
1091 debug("ehci intr queue: out of memory\n");
1094 result->current = result->first;
1095 result->last = result->first + queuesize - 1;
1096 result->tds = memalign(32, sizeof(struct qTD) * queuesize);
1098 debug("ehci intr queue: out of memory\n");
1101 memset(result->first, 0, sizeof(struct QH) * queuesize);
1102 memset(result->tds, 0, sizeof(struct qTD) * queuesize);
1104 for (i = 0; i < queuesize; i++) {
1105 struct QH *qh = result->first + i;
1106 struct qTD *td = result->tds + i;
1107 void **buf = &qh->buffer;
1109 qh->qh_link = (uint32_t)(qh+1) | QH_LINK_TYPE_QH;
1110 if (i == queuesize - 1)
1111 qh->qh_link = QH_LINK_TERMINATE;
1113 qh->qh_overlay.qt_next = (uint32_t)td;
1114 qh->qh_endpt1 = (0 << 28) | /* No NAK reload (ehci 4.9) */
1115 (usb_maxpacket(dev, pipe) << 16) | /* MPS */
1117 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
1118 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
1119 (usb_pipedevice(pipe) << 0);
1120 qh->qh_endpt2 = (1 << 30) | /* 1 Tx per mframe */
1121 (1 << 0); /* S-mask: microframe 0 */
1122 if (dev->speed == USB_SPEED_LOW ||
1123 dev->speed == USB_SPEED_FULL) {
1124 debug("TT: port: %d, hub address: %d\n",
1125 dev->portnr, dev->parent->devnum);
1126 qh->qh_endpt2 |= (dev->portnr << 23) |
1127 (dev->parent->devnum << 16) |
1128 (0x1c << 8); /* C-mask: microframes 2-4 */
1131 td->qt_next = QT_NEXT_TERMINATE;
1132 td->qt_altnext = QT_NEXT_TERMINATE;
1133 debug("communication direction is '%s'\n",
1134 usb_pipein(pipe) ? "in" : "out");
1135 td->qt_token = (elementsize << 16) |
1136 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
1138 td->qt_buffer[0] = (uint32_t)buffer + i * elementsize;
1139 td->qt_buffer[1] = (td->qt_buffer[0] + 0x1000) & ~0xfff;
1140 td->qt_buffer[2] = (td->qt_buffer[0] + 0x2000) & ~0xfff;
1141 td->qt_buffer[3] = (td->qt_buffer[0] + 0x3000) & ~0xfff;
1142 td->qt_buffer[4] = (td->qt_buffer[0] + 0x4000) & ~0xfff;
1144 *buf = buffer + i * elementsize;
1147 if (disable_periodic(ctrl) < 0) {
1148 debug("FATAL: periodic should never fail, but did");
1152 /* hook up to periodic list */
1153 struct QH *list = &ctrl->periodic_queue;
1154 result->last->qh_link = list->qh_link;
1155 list->qh_link = (uint32_t)result->first | QH_LINK_TYPE_QH;
1157 if (enable_periodic(ctrl) < 0) {
1158 debug("FATAL: periodic should never fail, but did");
1161 periodic_schedules++;
1163 debug("Exit create_int_queue\n");
1170 free(result->first);
1177 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1179 struct QH *cur = queue->current;
1181 /* depleted queue */
1183 debug("Exit poll_int_queue with completed queue\n");
1187 if (cur->qh_overlay.qt_token & 0x80) {
1188 debug("Exit poll_int_queue with no completed intr transfer. "
1189 "token is %x\n", cur->qh_overlay.qt_token);
1192 if (!(cur->qh_link & QH_LINK_TERMINATE))
1195 queue->current = NULL;
1196 debug("Exit poll_int_queue with completed intr transfer. "
1197 "token is %x at %p (first at %p)\n", cur->qh_overlay.qt_token,
1198 &cur->qh_overlay.qt_token, queue->first);
1202 /* Do not free buffers associated with QHs, they're owned by someone else */
1204 destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1206 struct ehci_ctrl *ctrl = dev->controller;
1208 unsigned long timeout;
1210 if (disable_periodic(ctrl) < 0) {
1211 debug("FATAL: periodic should never fail, but did");
1214 periodic_schedules--;
1216 struct QH *cur = &ctrl->periodic_queue;
1217 timeout = get_timer(0) + 500; /* abort after 500ms */
1218 while (!(cur->qh_link & QH_LINK_TERMINATE)) {
1219 debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
1220 if (NEXT_QH(cur) == queue->first) {
1221 debug("found candidate. removing from chain\n");
1222 cur->qh_link = queue->last->qh_link;
1227 if (get_timer(0) > timeout) {
1228 printf("Timeout destroying interrupt endpoint queue\n");
1234 if (periodic_schedules > 0) {
1235 result = enable_periodic(ctrl);
1237 debug("FATAL: periodic should never fail, but did");
1249 submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1250 int length, int interval)
1253 struct int_queue *queue;
1254 unsigned long timeout;
1255 int result = 0, ret;
1257 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1258 dev, pipe, buffer, length, interval);
1261 * Interrupt transfers requiring several transactions are not supported
1262 * because bInterval is ignored.
1264 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1265 * <= PKT_ALIGN if several qTDs are required, while the USB
1266 * specification does not constrain this for interrupt transfers. That
1267 * means that ehci_submit_async() would support interrupt transfers
1268 * requiring several transactions only as long as the transfer size does
1269 * not require more than a single qTD.
1271 if (length > usb_maxpacket(dev, pipe)) {
1272 printf("%s: Interrupt transfers requiring several "
1273 "transactions are not supported.\n", __func__);
1277 queue = create_int_queue(dev, pipe, 1, length, buffer);
1279 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1280 while ((backbuffer = poll_int_queue(dev, queue)) == NULL)
1281 if (get_timer(0) > timeout) {
1282 printf("Timeout poll on interrupt endpoint\n");
1283 result = -ETIMEDOUT;
1287 if (backbuffer != buffer) {
1288 debug("got wrong buffer back (%x instead of %x)\n",
1289 (uint32_t)backbuffer, (uint32_t)buffer);
1293 ret = destroy_int_queue(dev, queue);
1297 /* everything worked out fine */