2 * Copyright (c) 2007-2008, Juniper Networks, Inc.
3 * Copyright (c) 2008, Excito Elektronik i Skåne AB
4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2 of
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/byteorder.h>
26 #include <asm/unaligned.h>
31 #include <linux/compiler.h>
35 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
36 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
39 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
41 #define ALIGN_END_ADDR(type, ptr, size) \
42 ((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
44 static struct descriptor {
45 struct usb_hub_descriptor hub;
46 struct usb_device_descriptor device;
47 struct usb_linux_config_descriptor config;
48 struct usb_linux_interface_descriptor interface;
49 struct usb_endpoint_descriptor endpoint;
50 } __attribute__ ((packed)) descriptor = {
52 0x8, /* bDescLength */
53 0x29, /* bDescriptorType: hub descriptor */
54 2, /* bNrPorts -- runtime modified */
55 0, /* wHubCharacteristics */
56 10, /* bPwrOn2PwrGood */
57 0, /* bHubCntrCurrent */
58 {}, /* Device removable */
59 {} /* at most 7 ports! XXX */
63 1, /* bDescriptorType: UDESC_DEVICE */
64 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
65 9, /* bDeviceClass: UDCLASS_HUB */
66 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
67 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
68 64, /* bMaxPacketSize: 64 bytes */
69 0x0000, /* idVendor */
70 0x0000, /* idProduct */
71 cpu_to_le16(0x0100), /* bcdDevice */
72 1, /* iManufacturer */
74 0, /* iSerialNumber */
75 1 /* bNumConfigurations: 1 */
79 2, /* bDescriptorType: UDESC_CONFIG */
81 1, /* bNumInterface */
82 1, /* bConfigurationValue */
83 0, /* iConfiguration */
84 0x40, /* bmAttributes: UC_SELF_POWER */
89 4, /* bDescriptorType: UDESC_INTERFACE */
90 0, /* bInterfaceNumber */
91 0, /* bAlternateSetting */
92 1, /* bNumEndpoints */
93 9, /* bInterfaceClass: UICLASS_HUB */
94 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
95 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
100 5, /* bDescriptorType: UDESC_ENDPOINT */
101 0x81, /* bEndpointAddress:
102 * UE_DIR_IN | EHCI_INTR_ENDPT
104 3, /* bmAttributes: UE_INTERRUPT */
105 8, /* wMaxPacketSize */
110 #if defined(CONFIG_EHCI_IS_TDI)
111 #define ehci_is_TDI() (1)
113 #define ehci_is_TDI() (0)
116 int __ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
118 return PORTSC_PSPD(reg);
121 int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
122 __attribute__((weak, alias("__ehci_get_port_speed")));
124 void __ehci_set_usbmode(int index)
129 reg_ptr = (uint32_t *)((u8 *)&ehcic[index].hcor->or_usbcmd + USBMODE);
130 tmp = ehci_readl(reg_ptr);
131 tmp |= USBMODE_CM_HC;
132 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
135 ehci_writel(reg_ptr, tmp);
138 void ehci_set_usbmode(int index)
139 __attribute__((weak, alias("__ehci_set_usbmode")));
141 void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
146 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
147 __attribute__((weak, alias("__ehci_powerup_fixup")));
149 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
153 result = ehci_readl(ptr);
155 if (result == ~(uint32_t)0)
165 static int ehci_reset(int index)
170 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
171 cmd = (cmd & ~CMD_RUN) | CMD_RESET;
172 ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
173 ret = handshake((uint32_t *)&ehcic[index].hcor->or_usbcmd,
174 CMD_RESET, 0, 250 * 1000);
176 printf("EHCI fail to reset\n");
181 ehci_set_usbmode(index);
183 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
184 cmd = ehci_readl(&ehcic[index].hcor->or_txfilltuning);
185 cmd &= ~TXFIFO_THRESH_MASK;
186 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
187 ehci_writel(&ehcic[index].hcor->or_txfilltuning, cmd);
193 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
195 uint32_t delta, next;
196 uint32_t addr = (uint32_t)buf;
199 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
200 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
202 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
205 while (idx < QT_BUFFER_CNT) {
206 td->qt_buffer[idx] = cpu_to_hc32(addr);
207 td->qt_buffer_hi[idx] = 0;
208 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
217 if (idx == QT_BUFFER_CNT) {
218 printf("out of buffer pointers (%u bytes left)\n", sz);
225 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
227 #define QH_HIGH_SPEED 2
228 #define QH_FULL_SPEED 0
229 #define QH_LOW_SPEED 1
230 if (speed == USB_SPEED_HIGH)
231 return QH_HIGH_SPEED;
232 if (speed == USB_SPEED_LOW)
234 return QH_FULL_SPEED;
238 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
239 int length, struct devrequest *req)
241 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
245 volatile struct qTD *vtd;
248 uint32_t endpt, maxpacket, token, usbsts;
253 struct ehci_ctrl *ctrl = dev->controller;
255 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
256 buffer, length, req);
258 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
259 req->request, req->request,
260 req->requesttype, req->requesttype,
261 le16_to_cpu(req->value), le16_to_cpu(req->value),
262 le16_to_cpu(req->index));
264 #define PKT_ALIGN 512
266 * The USB transfer is split into qTD transfers. Eeach qTD transfer is
267 * described by a transfer descriptor (the qTD). The qTDs form a linked
268 * list with a queue head (QH).
270 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
271 * have its beginning in a qTD transfer and its end in the following
272 * one, so the qTD transfer lengths have to be chosen accordingly.
274 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
275 * single pages. The first data buffer can start at any offset within a
276 * page (not considering the cache-line alignment issues), while the
277 * following buffers must be page-aligned. There is no alignment
278 * constraint on the size of a qTD transfer.
281 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
283 if (length > 0 || req == NULL) {
285 * Determine the qTD transfer size that will be used for the
286 * data payload (not considering the first qTD transfer, which
287 * may be longer or shorter, and the final one, which may be
290 * In order to keep each packet within a qTD transfer, the qTD
291 * transfer size is aligned to PKT_ALIGN, which is a multiple of
292 * wMaxPacketSize (except in some cases for interrupt transfers,
293 * see comment in submit_int_msg()).
295 * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
296 * QT_BUFFER_CNT full pages will be used.
298 int xfr_sz = QT_BUFFER_CNT;
300 * However, if the input buffer is not aligned to PKT_ALIGN, the
301 * qTD transfer size will be one page shorter, and the first qTD
302 * data buffer of each transfer will be page-unaligned.
304 if ((uint32_t)buffer & (PKT_ALIGN - 1))
306 /* Convert the qTD transfer size to bytes. */
307 xfr_sz *= EHCI_PAGE_SIZE;
309 * Approximate by excess the number of qTDs that will be
310 * required for the data payload. The exact formula is way more
311 * complicated and saves at most 2 qTDs, i.e. a total of 128
314 qtd_count += 2 + length / xfr_sz;
317 * Threshold value based on the worst-case total size of the allocated qTDs for
318 * a mass-storage transfer of 65535 blocks of 512 bytes.
320 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
321 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
323 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
325 printf("unable to allocate TDs\n");
329 memset(qh, 0, sizeof(struct QH));
330 memset(qtd, 0, qtd_count * sizeof(*qtd));
332 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
335 * Setup QH (3.6 in ehci-r10.pdf)
337 * qh_link ................. 03-00 H
338 * qh_endpt1 ............... 07-04 H
339 * qh_endpt2 ............... 0B-08 H
341 * qh_overlay.qt_next ...... 13-10 H
342 * - qh_overlay.qt_altnext
344 qh->qh_link = cpu_to_hc32((uint32_t)&ctrl->qh_list | QH_LINK_TYPE_QH);
345 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
346 maxpacket = usb_maxpacket(dev, pipe);
347 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
348 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
349 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
350 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
351 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
352 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
353 qh->qh_endpt1 = cpu_to_hc32(endpt);
354 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_PORTNUM(dev->portnr) |
355 QH_ENDPT2_HUBADDR(dev->parent->devnum) |
356 QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
357 qh->qh_endpt2 = cpu_to_hc32(endpt);
358 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
360 tdp = &qh->qh_overlay.qt_next;
364 * Setup request qTD (3.5 in ehci-r10.pdf)
366 * qt_next ................ 03-00 H
367 * qt_altnext ............. 07-04 H
368 * qt_token ............... 0B-08 H
370 * [ buffer, buffer_hi ] loaded with "req".
372 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
373 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
374 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
375 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
376 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
377 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
378 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
379 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
380 printf("unable to construct SETUP TD\n");
383 /* Update previous qTD! */
384 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
385 tdp = &qtd[qtd_counter++].qt_next;
389 if (length > 0 || req == NULL) {
390 uint8_t *buf_ptr = buffer;
391 int left_length = length;
395 * Determine the size of this qTD transfer. By default,
396 * QT_BUFFER_CNT full pages can be used.
398 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
400 * However, if the input buffer is not page-aligned, the
401 * portion of the first page before the buffer start
402 * offset within that page is unusable.
404 xfr_bytes -= (uint32_t)buf_ptr & (EHCI_PAGE_SIZE - 1);
406 * In order to keep each packet within a qTD transfer,
407 * align the qTD transfer size to PKT_ALIGN.
409 xfr_bytes &= ~(PKT_ALIGN - 1);
411 * This transfer may be shorter than the available qTD
412 * transfer size that has just been computed.
414 xfr_bytes = min(xfr_bytes, left_length);
417 * Setup request qTD (3.5 in ehci-r10.pdf)
419 * qt_next ................ 03-00 H
420 * qt_altnext ............. 07-04 H
421 * qt_token ............... 0B-08 H
423 * [ buffer, buffer_hi ] loaded with "buffer".
425 qtd[qtd_counter].qt_next =
426 cpu_to_hc32(QT_NEXT_TERMINATE);
427 qtd[qtd_counter].qt_altnext =
428 cpu_to_hc32(QT_NEXT_TERMINATE);
429 token = QT_TOKEN_DT(toggle) |
430 QT_TOKEN_TOTALBYTES(xfr_bytes) |
431 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
433 QT_TOKEN_PID(usb_pipein(pipe) ?
434 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
435 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
436 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
437 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
439 printf("unable to construct DATA TD\n");
442 /* Update previous qTD! */
443 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
444 tdp = &qtd[qtd_counter++].qt_next;
446 * Data toggle has to be adjusted since the qTD transfer
447 * size is not always an even multiple of
450 if ((xfr_bytes / maxpacket) & 1)
452 buf_ptr += xfr_bytes;
453 left_length -= xfr_bytes;
454 } while (left_length > 0);
459 * Setup request qTD (3.5 in ehci-r10.pdf)
461 * qt_next ................ 03-00 H
462 * qt_altnext ............. 07-04 H
463 * qt_token ............... 0B-08 H
465 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
466 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
467 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
468 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
469 QT_TOKEN_PID(usb_pipein(pipe) ?
470 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
471 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
472 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
473 /* Update previous qTD! */
474 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
475 tdp = &qtd[qtd_counter++].qt_next;
478 ctrl->qh_list.qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH);
481 flush_dcache_range((uint32_t)&ctrl->qh_list,
482 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
483 flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1));
484 flush_dcache_range((uint32_t)qtd,
485 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
487 /* Set async. queue head pointer. */
488 ehci_writel(&ctrl->hcor->or_asynclistaddr, (uint32_t)&ctrl->qh_list);
490 usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
491 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
493 /* Enable async. schedule. */
494 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
496 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
498 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
501 printf("EHCI fail timeout STS_ASS set\n");
505 /* Wait for TDs to be processed. */
507 vtd = &qtd[qtd_counter - 1];
508 timeout = USB_TIMEOUT_MS(pipe);
510 /* Invalidate dcache */
511 invalidate_dcache_range((uint32_t)&ctrl->qh_list,
512 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
513 invalidate_dcache_range((uint32_t)qh,
514 ALIGN_END_ADDR(struct QH, qh, 1));
515 invalidate_dcache_range((uint32_t)qtd,
516 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
518 token = hc32_to_cpu(vtd->qt_token);
519 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
522 } while (get_timer(ts) < timeout);
525 * Invalidate the memory area occupied by buffer
526 * Don't try to fix the buffer alignment, if it isn't properly
527 * aligned it's upper layer's fault so let invalidate_dcache_range()
528 * vow about it. But we have to fix the length as it's actual
529 * transfer length and can be unaligned. This is potentially
530 * dangerous operation, it's responsibility of the calling
531 * code to make sure enough space is reserved.
533 invalidate_dcache_range((uint32_t)buffer,
534 ALIGN((uint32_t)buffer + length, ARCH_DMA_MINALIGN));
536 /* Check that the TD processing happened */
537 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
538 printf("EHCI timed out on TD - token=%#x\n", token);
540 /* Disable async schedule. */
541 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
543 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
545 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
548 printf("EHCI fail timeout STS_ASS reset\n");
552 token = hc32_to_cpu(qh->qh_overlay.qt_token);
553 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
554 debug("TOKEN=%#x\n", token);
555 switch (QT_TOKEN_GET_STATUS(token) &
556 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
558 toggle = QT_TOKEN_GET_DT(token);
559 usb_settoggle(dev, usb_pipeendpoint(pipe),
560 usb_pipeout(pipe), toggle);
563 case QT_TOKEN_STATUS_HALTED:
564 dev->status = USB_ST_STALLED;
566 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
567 case QT_TOKEN_STATUS_DATBUFERR:
568 dev->status = USB_ST_BUF_ERR;
570 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
571 case QT_TOKEN_STATUS_BABBLEDET:
572 dev->status = USB_ST_BABBLE_DET;
575 dev->status = USB_ST_CRC_ERR;
576 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
577 dev->status |= USB_ST_STALLED;
580 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
583 #ifndef CONFIG_USB_EHCI_FARADAY
584 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
585 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
586 ehci_readl(&ctrl->hcor->or_portsc[0]),
587 ehci_readl(&ctrl->hcor->or_portsc[1]));
592 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
599 __weak uint32_t *ehci_get_portsc_register(struct ehci_hcor *hcor, int port)
601 if (port < 0 || port >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
602 /* Printing the message would cause a scan failure! */
603 debug("The request port(%u) is not configured\n", port);
607 return (uint32_t *)&hcor->or_portsc[port];
611 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
612 int length, struct devrequest *req)
619 uint32_t *status_reg;
620 int port = le16_to_cpu(req->index) & 0xff;
621 struct ehci_ctrl *ctrl = dev->controller;
625 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
626 req->request, req->request,
627 req->requesttype, req->requesttype,
628 le16_to_cpu(req->value), le16_to_cpu(req->index));
630 typeReq = req->request | req->requesttype << 8;
633 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
634 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
635 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
636 status_reg = ehci_get_portsc_register(ctrl->hcor, port - 1);
646 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
647 switch (le16_to_cpu(req->value) >> 8) {
649 debug("USB_DT_DEVICE request\n");
650 srcptr = &descriptor.device;
651 srclen = descriptor.device.bLength;
654 debug("USB_DT_CONFIG config\n");
655 srcptr = &descriptor.config;
656 srclen = descriptor.config.bLength +
657 descriptor.interface.bLength +
658 descriptor.endpoint.bLength;
661 debug("USB_DT_STRING config\n");
662 switch (le16_to_cpu(req->value) & 0xff) {
663 case 0: /* Language */
668 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
671 case 2: /* Product */
672 srcptr = "\52\3E\0H\0C\0I\0 "
674 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
678 debug("unknown value DT_STRING %x\n",
679 le16_to_cpu(req->value));
684 debug("unknown value %x\n", le16_to_cpu(req->value));
688 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
689 switch (le16_to_cpu(req->value) >> 8) {
691 debug("USB_DT_HUB config\n");
692 srcptr = &descriptor.hub;
693 srclen = descriptor.hub.bLength;
696 debug("unknown value %x\n", le16_to_cpu(req->value));
700 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
701 debug("USB_REQ_SET_ADDRESS\n");
702 ctrl->rootdev = le16_to_cpu(req->value);
704 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
705 debug("USB_REQ_SET_CONFIGURATION\n");
708 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
709 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
714 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
715 memset(tmpbuf, 0, 4);
716 reg = ehci_readl(status_reg);
717 if (reg & EHCI_PS_CS)
718 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
719 if (reg & EHCI_PS_PE)
720 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
721 if (reg & EHCI_PS_SUSP)
722 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
723 if (reg & EHCI_PS_OCA)
724 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
725 if (reg & EHCI_PS_PR)
726 tmpbuf[0] |= USB_PORT_STAT_RESET;
727 if (reg & EHCI_PS_PP)
728 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
731 switch (ehci_get_port_speed(ctrl->hcor, reg)) {
735 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
739 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
743 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
746 if (reg & EHCI_PS_CSC)
747 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
748 if (reg & EHCI_PS_PEC)
749 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
750 if (reg & EHCI_PS_OCC)
751 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
752 if (ctrl->portreset & (1 << port))
753 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
758 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
759 reg = ehci_readl(status_reg);
760 reg &= ~EHCI_PS_CLEAR;
761 switch (le16_to_cpu(req->value)) {
762 case USB_PORT_FEAT_ENABLE:
764 ehci_writel(status_reg, reg);
766 case USB_PORT_FEAT_POWER:
767 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
769 ehci_writel(status_reg, reg);
772 case USB_PORT_FEAT_RESET:
773 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
775 EHCI_PS_IS_LOWSPEED(reg)) {
776 /* Low speed device, give up ownership. */
777 debug("port %d low speed --> companion\n",
780 ehci_writel(status_reg, reg);
787 ehci_writel(status_reg, reg);
789 * caller must wait, then call GetPortStatus
790 * usb 2.0 specification say 50 ms resets on
793 ehci_powerup_fixup(status_reg, ®);
795 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
797 * A host controller must terminate the reset
798 * and stabilize the state of the port within
801 ret = handshake(status_reg, EHCI_PS_PR, 0,
804 ctrl->portreset |= 1 << port;
806 printf("port(%d) reset error\n",
810 case USB_PORT_FEAT_TEST:
812 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
813 ehci_writel(status_reg, reg);
816 debug("unknown feature %x\n", le16_to_cpu(req->value));
819 /* unblock posted writes */
820 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
822 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
823 reg = ehci_readl(status_reg);
824 reg &= ~EHCI_PS_CLEAR;
825 switch (le16_to_cpu(req->value)) {
826 case USB_PORT_FEAT_ENABLE:
829 case USB_PORT_FEAT_C_ENABLE:
832 case USB_PORT_FEAT_POWER:
833 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
836 case USB_PORT_FEAT_C_CONNECTION:
839 case USB_PORT_FEAT_OVER_CURRENT:
842 case USB_PORT_FEAT_C_RESET:
843 ctrl->portreset &= ~(1 << port);
846 debug("unknown feature %x\n", le16_to_cpu(req->value));
849 ehci_writel(status_reg, reg);
850 /* unblock posted write */
851 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
854 debug("Unknown request\n");
859 len = min3(srclen, le16_to_cpu(req->length), length);
860 if (srcptr != NULL && len > 0)
861 memcpy(buffer, srcptr, len);
870 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
871 req->requesttype, req->request, le16_to_cpu(req->value),
872 le16_to_cpu(req->index), le16_to_cpu(req->length));
875 dev->status = USB_ST_STALLED;
879 int usb_lowlevel_stop(int index)
881 return ehci_hcd_stop(index);
884 int usb_lowlevel_init(int index, void **controller)
892 if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor))
895 /* EHCI spec section 4.1 */
896 if (ehci_reset(index))
899 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
900 if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor))
903 /* Set the high address word (aka segment) for 64-bit controller */
904 if (ehci_readl(&ehcic[index].hccr->cr_hccparams) & 1)
905 ehci_writel(ehcic[index].hcor->or_ctrldssegment, 0);
907 qh_list = &ehcic[index].qh_list;
909 /* Set head of reclaim list */
910 memset(qh_list, 0, sizeof(*qh_list));
911 qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
912 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
913 QH_ENDPT1_EPS(USB_SPEED_HIGH));
914 qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
915 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
916 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
917 qh_list->qh_overlay.qt_token =
918 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
920 flush_dcache_range((uint32_t)qh_list,
921 ALIGN_END_ADDR(struct QH, qh_list, 1));
923 /* Set async. queue head pointer. */
924 ehci_writel(&ehcic[index].hcor->or_asynclistaddr, (uint32_t)qh_list);
927 * Set up periodic list
928 * Step 1: Parent QH for all periodic transfers.
930 periodic = &ehcic[index].periodic_queue;
931 memset(periodic, 0, sizeof(*periodic));
932 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
933 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
934 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
936 flush_dcache_range((uint32_t)periodic,
937 ALIGN_END_ADDR(struct QH, periodic, 1));
940 * Step 2: Setup frame-list: Every microframe, USB tries the same list.
941 * In particular, device specifications on polling frequency
942 * are disregarded. Keyboards seem to send NAK/NYet reliably
943 * when polled with an empty buffer.
945 * Split Transactions will be spread across microframes using
948 if (ehcic[index].periodic_list == NULL)
949 ehcic[index].periodic_list = memalign(4096, 1024 * 4);
951 if (!ehcic[index].periodic_list)
953 for (i = 0; i < 1024; i++) {
954 ehcic[index].periodic_list[i] = (uint32_t)periodic
958 flush_dcache_range((uint32_t)ehcic[index].periodic_list,
959 ALIGN_END_ADDR(uint32_t, ehcic[index].periodic_list,
962 /* Set periodic list base address */
963 ehci_writel(&ehcic[index].hcor->or_periodiclistbase,
964 (uint32_t)ehcic[index].periodic_list);
966 reg = ehci_readl(&ehcic[index].hccr->cr_hcsparams);
967 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
968 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
969 /* Port Indicators */
970 if (HCS_INDICATOR(reg))
971 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
972 | 0x80, &descriptor.hub.wHubCharacteristics);
973 /* Port Power Control */
975 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
976 | 0x01, &descriptor.hub.wHubCharacteristics);
978 /* Start the host controller. */
979 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
981 * Philips, Intel, and maybe others need CMD_RUN before the
982 * root hub will detect new devices (why?); NEC doesn't
984 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
986 ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
988 #ifndef CONFIG_USB_EHCI_FARADAY
989 /* take control over the ports */
990 cmd = ehci_readl(&ehcic[index].hcor->or_configflag);
992 ehci_writel(&ehcic[index].hcor->or_configflag, cmd);
995 /* unblock posted write */
996 cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
998 reg = HC_VERSION(ehci_readl(&ehcic[index].hccr->cr_capbase));
999 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
1001 ehcic[index].rootdev = 0;
1003 *controller = &ehcic[index];
1008 submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1012 if (usb_pipetype(pipe) != PIPE_BULK) {
1013 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1016 return ehci_submit_async(dev, pipe, buffer, length, NULL);
1020 submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1021 int length, struct devrequest *setup)
1023 struct ehci_ctrl *ctrl = dev->controller;
1025 if (usb_pipetype(pipe) != PIPE_CONTROL) {
1026 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
1030 if (usb_pipedevice(pipe) == ctrl->rootdev) {
1032 dev->speed = USB_SPEED_HIGH;
1033 return ehci_submit_root(dev, pipe, buffer, length, setup);
1035 return ehci_submit_async(dev, pipe, buffer, length, setup);
1045 #define NEXT_QH(qh) (struct QH *)((qh)->qh_link & ~0x1f)
1048 enable_periodic(struct ehci_ctrl *ctrl)
1051 struct ehci_hcor *hcor = ctrl->hcor;
1054 cmd = ehci_readl(&hcor->or_usbcmd);
1056 ehci_writel(&hcor->or_usbcmd, cmd);
1058 ret = handshake((uint32_t *)&hcor->or_usbsts,
1059 STS_PSS, STS_PSS, 100 * 1000);
1061 printf("EHCI failed: timeout when enabling periodic list\n");
1069 disable_periodic(struct ehci_ctrl *ctrl)
1072 struct ehci_hcor *hcor = ctrl->hcor;
1075 cmd = ehci_readl(&hcor->or_usbcmd);
1077 ehci_writel(&hcor->or_usbcmd, cmd);
1079 ret = handshake((uint32_t *)&hcor->or_usbsts,
1080 STS_PSS, 0, 100 * 1000);
1082 printf("EHCI failed: timeout when disabling periodic list\n");
1088 static int periodic_schedules;
1091 create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize,
1092 int elementsize, void *buffer)
1094 struct ehci_ctrl *ctrl = dev->controller;
1095 struct int_queue *result = NULL;
1098 debug("Enter create_int_queue\n");
1099 if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1100 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1104 /* limit to 4 full pages worth of data -
1105 * we can safely fit them in a single TD,
1106 * no matter the alignment
1108 if (elementsize >= 16384) {
1109 debug("too large elements for interrupt transfers\n");
1113 result = malloc(sizeof(*result));
1115 debug("ehci intr queue: out of memory\n");
1118 result->first = memalign(32, sizeof(struct QH) * queuesize);
1119 if (!result->first) {
1120 debug("ehci intr queue: out of memory\n");
1123 result->current = result->first;
1124 result->last = result->first + queuesize - 1;
1125 result->tds = memalign(32, sizeof(struct qTD) * queuesize);
1127 debug("ehci intr queue: out of memory\n");
1130 memset(result->first, 0, sizeof(struct QH) * queuesize);
1131 memset(result->tds, 0, sizeof(struct qTD) * queuesize);
1133 for (i = 0; i < queuesize; i++) {
1134 struct QH *qh = result->first + i;
1135 struct qTD *td = result->tds + i;
1136 void **buf = &qh->buffer;
1138 qh->qh_link = (uint32_t)(qh+1) | QH_LINK_TYPE_QH;
1139 if (i == queuesize - 1)
1140 qh->qh_link = QH_LINK_TERMINATE;
1142 qh->qh_overlay.qt_next = (uint32_t)td;
1143 qh->qh_endpt1 = (0 << 28) | /* No NAK reload (ehci 4.9) */
1144 (usb_maxpacket(dev, pipe) << 16) | /* MPS */
1146 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
1147 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
1148 (usb_pipedevice(pipe) << 0);
1149 qh->qh_endpt2 = (1 << 30) | /* 1 Tx per mframe */
1150 (1 << 0); /* S-mask: microframe 0 */
1151 if (dev->speed == USB_SPEED_LOW ||
1152 dev->speed == USB_SPEED_FULL) {
1153 debug("TT: port: %d, hub address: %d\n",
1154 dev->portnr, dev->parent->devnum);
1155 qh->qh_endpt2 |= (dev->portnr << 23) |
1156 (dev->parent->devnum << 16) |
1157 (0x1c << 8); /* C-mask: microframes 2-4 */
1160 td->qt_next = QT_NEXT_TERMINATE;
1161 td->qt_altnext = QT_NEXT_TERMINATE;
1162 debug("communication direction is '%s'\n",
1163 usb_pipein(pipe) ? "in" : "out");
1164 td->qt_token = (elementsize << 16) |
1165 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
1167 td->qt_buffer[0] = (uint32_t)buffer + i * elementsize;
1168 td->qt_buffer[1] = (td->qt_buffer[0] + 0x1000) & ~0xfff;
1169 td->qt_buffer[2] = (td->qt_buffer[0] + 0x2000) & ~0xfff;
1170 td->qt_buffer[3] = (td->qt_buffer[0] + 0x3000) & ~0xfff;
1171 td->qt_buffer[4] = (td->qt_buffer[0] + 0x4000) & ~0xfff;
1173 *buf = buffer + i * elementsize;
1176 flush_dcache_range((uint32_t)buffer,
1177 ALIGN_END_ADDR(char, buffer,
1178 queuesize * elementsize));
1179 flush_dcache_range((uint32_t)result->first,
1180 ALIGN_END_ADDR(struct QH, result->first,
1182 flush_dcache_range((uint32_t)result->tds,
1183 ALIGN_END_ADDR(struct qTD, result->tds,
1186 if (disable_periodic(ctrl) < 0) {
1187 debug("FATAL: periodic should never fail, but did");
1191 /* hook up to periodic list */
1192 struct QH *list = &ctrl->periodic_queue;
1193 result->last->qh_link = list->qh_link;
1194 list->qh_link = (uint32_t)result->first | QH_LINK_TYPE_QH;
1196 flush_dcache_range((uint32_t)result->last,
1197 ALIGN_END_ADDR(struct QH, result->last, 1));
1198 flush_dcache_range((uint32_t)list,
1199 ALIGN_END_ADDR(struct QH, list, 1));
1201 if (enable_periodic(ctrl) < 0) {
1202 debug("FATAL: periodic should never fail, but did");
1205 periodic_schedules++;
1207 debug("Exit create_int_queue\n");
1214 free(result->first);
1221 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1223 struct QH *cur = queue->current;
1225 /* depleted queue */
1227 debug("Exit poll_int_queue with completed queue\n");
1231 invalidate_dcache_range((uint32_t)cur,
1232 ALIGN_END_ADDR(struct QH, cur, 1));
1233 if (cur->qh_overlay.qt_token & 0x80) {
1234 debug("Exit poll_int_queue with no completed intr transfer. "
1235 "token is %x\n", cur->qh_overlay.qt_token);
1238 if (!(cur->qh_link & QH_LINK_TERMINATE))
1241 queue->current = NULL;
1242 debug("Exit poll_int_queue with completed intr transfer. "
1243 "token is %x at %p (first at %p)\n", cur->qh_overlay.qt_token,
1244 &cur->qh_overlay.qt_token, queue->first);
1248 /* Do not free buffers associated with QHs, they're owned by someone else */
1250 destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1252 struct ehci_ctrl *ctrl = dev->controller;
1254 unsigned long timeout;
1256 if (disable_periodic(ctrl) < 0) {
1257 debug("FATAL: periodic should never fail, but did");
1260 periodic_schedules--;
1262 struct QH *cur = &ctrl->periodic_queue;
1263 timeout = get_timer(0) + 500; /* abort after 500ms */
1264 while (!(cur->qh_link & QH_LINK_TERMINATE)) {
1265 debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
1266 if (NEXT_QH(cur) == queue->first) {
1267 debug("found candidate. removing from chain\n");
1268 cur->qh_link = queue->last->qh_link;
1273 if (get_timer(0) > timeout) {
1274 printf("Timeout destroying interrupt endpoint queue\n");
1280 if (periodic_schedules > 0) {
1281 result = enable_periodic(ctrl);
1283 debug("FATAL: periodic should never fail, but did");
1295 submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1296 int length, int interval)
1299 struct int_queue *queue;
1300 unsigned long timeout;
1301 int result = 0, ret;
1303 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1304 dev, pipe, buffer, length, interval);
1307 * Interrupt transfers requiring several transactions are not supported
1308 * because bInterval is ignored.
1310 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1311 * <= PKT_ALIGN if several qTDs are required, while the USB
1312 * specification does not constrain this for interrupt transfers. That
1313 * means that ehci_submit_async() would support interrupt transfers
1314 * requiring several transactions only as long as the transfer size does
1315 * not require more than a single qTD.
1317 if (length > usb_maxpacket(dev, pipe)) {
1318 printf("%s: Interrupt transfers requiring several "
1319 "transactions are not supported.\n", __func__);
1323 queue = create_int_queue(dev, pipe, 1, length, buffer);
1325 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1326 while ((backbuffer = poll_int_queue(dev, queue)) == NULL)
1327 if (get_timer(0) > timeout) {
1328 printf("Timeout poll on interrupt endpoint\n");
1329 result = -ETIMEDOUT;
1333 if (backbuffer != buffer) {
1334 debug("got wrong buffer back (%x instead of %x)\n",
1335 (uint32_t)backbuffer, (uint32_t)buffer);
1339 invalidate_dcache_range((uint32_t)buffer,
1340 ALIGN_END_ADDR(char, buffer, length));
1342 ret = destroy_int_queue(dev, queue);
1346 /* everything worked out fine */