2 * Copyright (c) 2011 The Chromium OS Authors.
3 * Copyright (c) 2009-2013 NVIDIA Corporation
4 * Copyright (c) 2013 Lucas Stach
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
12 #include <asm-generic/gpio.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch-tegra/usb.h>
15 #include <asm/arch-tegra/clk_rst.h>
23 #define USB1_ADDR_MASK 0xFFFF0000
25 #define HOSTPC1_DEVLC 0x84
26 #define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3)
28 #ifdef CONFIG_USB_ULPI
29 #ifndef CONFIG_USB_ULPI_VIEWPORT
30 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \
31 define CONFIG_USB_ULPI_VIEWPORT"
36 USB_PORTS_MAX = 3, /* Maximum ports we allow */
39 /* Parameters we need for USB */
41 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */
42 PARAM_DIVM, /* PLL INPUT DIVIDER */
43 PARAM_DIVP, /* POST DIVIDER (2^N) */
44 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */
45 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */
46 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */
47 PARAM_STABLE_COUNT, /* PLL-U STABLE count */
48 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */
49 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */
50 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */
51 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */
56 /* Possible port types (dual role mode) */
59 DR_MODE_HOST, /* supports host operation */
60 DR_MODE_DEVICE, /* supports device operation */
61 DR_MODE_OTG, /* supports both */
72 /* Information about a USB port */
74 struct usb_ctlr *reg; /* address of registers in physical memory */
75 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */
76 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */
77 unsigned enabled:1; /* 1 to enable, 0 to disable */
78 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
79 unsigned initialized:1; /* has this port already been initialized? */
80 enum usb_ctlr_type type;
81 enum usb_init_type init_type;
82 enum dr_mode dr_mode; /* dual role mode */
83 enum periph_id periph_id;/* peripheral id */
84 struct gpio_desc vbus_gpio; /* GPIO for vbus enable */
85 struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */
88 static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
89 static unsigned port_count; /* Number of available ports */
90 /* Port that needs to clear CSC after Port Reset */
91 static u32 port_addr_clear_csc;
94 * This table has USB timing parameters for each Oscillator frequency we
95 * support. There are four sets of values:
97 * 1. PLLU configuration information (reference clock is osc/clk_m and
98 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
100 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
101 * ----------------------------------------------------------------------
102 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0)
103 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a)
104 * Filter frequency (MHz) 1 4.8 6 2
105 * CPCON 1100b 0011b 1100b 1100b
108 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
110 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
111 * ---------------------------------------------------------------------------
112 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04)
113 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66)
114 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09)
115 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE)
117 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
118 * SessEnd. Each of these signals have their own debouncer and for each of
119 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
122 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
123 * 0xffff -> No debouncing at all
124 * <n> ms = <n> *1000 / (1/19.2MHz) / 4
126 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have:
127 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0
129 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
130 * values, so we can keep those to default.
132 * 4. The 20 microsecond delay after bias cell operation.
134 static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
135 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
136 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
137 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
138 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
139 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
142 static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
143 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
144 { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 },
145 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 },
146 { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 },
147 { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
150 static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
151 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
152 { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 },
153 { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 },
154 { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 },
155 { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB }
158 /* UTMIP Idle Wait Delay */
159 static const u8 utmip_idle_wait_delay = 17;
161 /* UTMIP Elastic limit */
162 static const u8 utmip_elastic_limit = 16;
164 /* UTMIP High Speed Sync Start Delay */
165 static const u8 utmip_hs_sync_start_delay = 9;
167 struct fdt_usb_controller {
169 /* flag to determine whether controller supports hostpc register */
171 const unsigned *pll_parameter;
174 static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = {
176 .compat = COMPAT_NVIDIA_TEGRA20_USB,
178 .pll_parameter = (const unsigned *)T20_usb_pll,
181 .compat = COMPAT_NVIDIA_TEGRA30_USB,
183 .pll_parameter = (const unsigned *)T30_usb_pll,
186 .compat = COMPAT_NVIDIA_TEGRA114_USB,
188 .pll_parameter = (const unsigned *)T114_usb_pll,
192 static struct fdt_usb_controller *controller;
195 * A known hardware issue where Connect Status Change bit of PORTSC register
196 * of USB1 controller will be set after Port Reset.
197 * We have to clear it in order for later device enumeration to proceed.
198 * This ehci_powerup_fixup overrides the weak function ehci_powerup_fixup
201 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
204 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */
205 if (controller->has_hostpc)
208 if (((unsigned long)status_reg & TEGRA_USB_ADDR_MASK) != port_addr_clear_csc)
210 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */
211 if (ehci_readl(status_reg) & EHCI_PS_CSC)
216 * This ehci_set_usbmode overrides the weak function ehci_set_usbmode
219 void ehci_set_usbmode(int index)
221 struct fdt_usb *config;
222 struct usb_ctlr *usbctlr;
225 config = &port[index];
226 usbctlr = config->reg;
228 tmp = ehci_readl(&usbctlr->usb_mode);
229 tmp |= USBMODE_CM_HC;
230 ehci_writel(&usbctlr->usb_mode, tmp);
234 * This ehci_get_port_speed overrides the weak function ehci_get_port_speed
237 int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
242 if (controller->has_hostpc) {
243 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd +
245 tmp = ehci_readl(reg_ptr);
246 return HOSTPC1_PSPD(tmp);
248 return PORTSC_PSPD(reg);
251 /* Set up VBUS for host/device mode */
252 static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init)
255 * If we are an OTG port initializing in host mode,
256 * check if remote host is driving VBus and bail out in this case.
258 if (init == USB_INIT_HOST &&
259 config->dr_mode == DR_MODE_OTG &&
260 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) {
261 printf("tegrausb: VBUS input active; not enabling as host\n");
265 if (dm_gpio_is_valid(&config->vbus_gpio)) {
268 vbus_value = (init == USB_INIT_HOST);
269 dm_gpio_set_value(&config->vbus_gpio, vbus_value);
271 debug("set_up_vbus: GPIO %d %d\n",
272 gpio_get_number(&config->vbus_gpio), vbus_value);
276 void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr)
278 /* Reset the USB controller with 2us delay */
279 reset_periph(config->periph_id, 2);
282 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under
285 if (config->has_legacy_mode)
286 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
288 /* Put UTMIP1/3 in reset */
289 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
291 /* Enable the UTMIP PHY */
293 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
296 static const unsigned *get_pll_timing(struct fdt_usb_controller *controller)
298 const unsigned *timing;
300 timing = controller->pll_parameter +
301 clock_get_osc_freq() * PARAM_COUNT;
306 /* select the PHY to use with a USB controller */
307 static void init_phy_mux(struct fdt_usb *config, uint pts,
308 enum usb_init_type init)
310 struct usb_ctlr *usbctlr = config->reg;
312 #if defined(CONFIG_TEGRA20)
313 if (config->periph_id == PERIPH_ID_USBD) {
314 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK,
316 clrbits_le32(&usbctlr->port_sc1, STS1);
318 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
320 clrbits_le32(&usbctlr->port_sc1, STS);
323 /* Set to Host mode (if applicable) after Controller Reset was done */
324 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC,
325 (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0);
327 * Select PHY interface after setting host mode.
328 * For device mode, the ordering requirement is not an issue, since
329 * only the first USB controller supports device mode, and that USB
330 * controller can only talk to a UTMI PHY, so the PHY selection is
331 * already made at reset time, so this write is a no-op.
333 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
335 clrbits_le32(&usbctlr->hostpc1_devlc, STS);
339 /* set up the UTMI USB controller with the parameters provided */
340 static int init_utmi_usb_controller(struct fdt_usb *config,
341 enum usb_init_type init)
343 struct fdt_usb_controller *controller;
344 u32 b_sess_valid_mask, val;
346 const unsigned *timing;
347 struct usb_ctlr *usbctlr = config->reg;
348 struct clk_rst_ctlr *clkrst;
349 struct usb_ctlr *usb1ctlr;
351 clock_enable(config->periph_id);
353 /* Reset the usb controller */
354 usbf_reset_controller(config, usbctlr);
356 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
357 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
359 /* Follow the crystal clock disable by >100ns delay */
362 b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN);
363 clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask,
364 (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0);
367 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
368 * mux must be switched to actually use a_sess_vld threshold.
370 if (config->dr_mode == DR_MODE_OTG &&
371 dm_gpio_is_valid(&config->vbus_gpio))
372 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
374 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
376 controller = &fdt_usb_controllers[config->type];
377 debug("controller=%p, type=%d\n", controller, config->type);
380 * PLL Delay CONFIGURATION settings. The following parameters control
381 * the bring up of the plls.
383 timing = get_pll_timing(controller);
385 if (!controller->has_hostpc) {
386 val = readl(&usbctlr->utmip_misc_cfg1);
387 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
388 timing[PARAM_STABLE_COUNT] <<
389 UTMIP_PLLU_STABLE_COUNT_SHIFT);
390 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
391 timing[PARAM_ACTIVE_DELAY_COUNT] <<
392 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
393 writel(val, &usbctlr->utmip_misc_cfg1);
395 /* Set PLL enable delay count and crystal frequency count */
396 val = readl(&usbctlr->utmip_pll_cfg1);
397 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
398 timing[PARAM_ENABLE_DELAY_COUNT] <<
399 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
400 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
401 timing[PARAM_XTAL_FREQ_COUNT] <<
402 UTMIP_XTAL_FREQ_COUNT_SHIFT);
403 writel(val, &usbctlr->utmip_pll_cfg1);
405 clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
407 val = readl(&clkrst->crc_utmip_pll_cfg2);
408 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
409 timing[PARAM_STABLE_COUNT] <<
410 UTMIP_PLLU_STABLE_COUNT_SHIFT);
411 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
412 timing[PARAM_ACTIVE_DELAY_COUNT] <<
413 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
414 writel(val, &clkrst->crc_utmip_pll_cfg2);
416 /* Set PLL enable delay count and crystal frequency count */
417 val = readl(&clkrst->crc_utmip_pll_cfg1);
418 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
419 timing[PARAM_ENABLE_DELAY_COUNT] <<
420 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
421 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
422 timing[PARAM_XTAL_FREQ_COUNT] <<
423 UTMIP_XTAL_FREQ_COUNT_SHIFT);
424 writel(val, &clkrst->crc_utmip_pll_cfg1);
426 /* Disable Power Down state for PLL */
427 clrbits_le32(&clkrst->crc_utmip_pll_cfg1,
428 PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN |
429 PLL_ACTIVE_POWERDOWN);
431 /* Recommended PHY settings for EYE diagram */
432 val = readl(&usbctlr->utmip_xcvr_cfg0);
433 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK,
434 0x4 << UTMIP_XCVR_SETUP_SHIFT);
435 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK,
436 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT);
437 clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK,
438 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT);
439 writel(val, &usbctlr->utmip_xcvr_cfg0);
440 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1,
441 UTMIP_XCVR_TERM_RANGE_ADJ_MASK,
442 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT);
444 /* Some registers can be controlled from USB1 only. */
445 if (config->periph_id != PERIPH_ID_USBD) {
446 clock_enable(PERIPH_ID_USBD);
447 /* Disable Reset if in Reset state */
448 reset_set_enable(PERIPH_ID_USBD, 0);
450 usb1ctlr = (struct usb_ctlr *)
451 ((unsigned long)config->reg & USB1_ADDR_MASK);
452 val = readl(&usb1ctlr->utmip_bias_cfg0);
453 setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB);
454 clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK,
455 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT);
456 clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK,
457 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT);
458 writel(val, &usb1ctlr->utmip_bias_cfg0);
460 /* Miscellaneous setting mentioned in Programming Guide */
461 clrbits_le32(&usbctlr->utmip_misc_cfg0,
462 UTMIP_SUSPEND_EXIT_ON_EDGE);
465 /* Setting the tracking length time */
466 clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
467 UTMIP_BIAS_PDTRK_COUNT_MASK,
468 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
470 /* Program debounce time for VBUS to become valid */
471 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
472 UTMIP_DEBOUNCE_CFG0_MASK,
473 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
475 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
477 /* Disable battery charge enabling bit */
478 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
480 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
481 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
484 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
485 * Setting these fields, together with default values of the
486 * other fields, results in programming the registers below as
488 * UTMIP_HSRX_CFG0 = 0x9168c000
489 * UTMIP_HSRX_CFG1 = 0x13
492 /* Set PLL enable delay count and Crystal frequency count */
493 val = readl(&usbctlr->utmip_hsrx_cfg0);
494 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
495 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
496 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
497 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
498 writel(val, &usbctlr->utmip_hsrx_cfg0);
500 /* Configure the UTMIP_HS_SYNC_START_DLY */
501 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
502 UTMIP_HS_SYNC_START_DLY_MASK,
503 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
505 /* Preceed the crystal clock disable by >100ns delay. */
508 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
509 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
511 if (controller->has_hostpc) {
512 if (config->periph_id == PERIPH_ID_USBD)
513 clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
514 UTMIP_FORCE_PD_SAMP_A_POWERDOWN);
515 if (config->periph_id == PERIPH_ID_USB2)
516 clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
517 UTMIP_FORCE_PD_SAMP_B_POWERDOWN);
518 if (config->periph_id == PERIPH_ID_USB3)
519 clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
520 UTMIP_FORCE_PD_SAMP_C_POWERDOWN);
522 /* Finished the per-controller init. */
524 /* De-assert UTMIP_RESET to bring out of reset. */
525 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
527 /* Wait for the phy clock to become valid in 100 ms */
528 for (loop_count = 100000; loop_count != 0; loop_count--) {
529 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
536 /* Disable ICUSB FS/LS transceiver */
537 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
539 /* Select UTMI parallel interface */
540 init_phy_mux(config, PTS_UTMI, init);
542 /* Deassert power down state */
543 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
544 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
545 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
546 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
548 if (controller->has_hostpc) {
550 * BIAS Pad Power Down is common among all 3 USB
551 * controllers and can be controlled from USB1 only.
553 usb1ctlr = (struct usb_ctlr *)
554 ((unsigned long)config->reg & USB1_ADDR_MASK);
555 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD);
557 clrbits_le32(&usb1ctlr->utmip_bias_cfg1,
558 UTMIP_FORCE_PDTRK_POWERDOWN);
563 #ifdef CONFIG_USB_ULPI
564 /* if board file does not set a ULPI reference frequency we default to 24MHz */
565 #ifndef CONFIG_ULPI_REF_CLK
566 #define CONFIG_ULPI_REF_CLK 24000000
569 /* set up the ULPI USB controller with the parameters provided */
570 static int init_ulpi_usb_controller(struct fdt_usb *config,
571 enum usb_init_type init)
575 struct ulpi_viewport ulpi_vp;
576 struct usb_ctlr *usbctlr = config->reg;
578 /* set up ULPI reference clock on pllp_out4 */
579 clock_enable(PERIPH_ID_DEV2_OUT);
580 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK);
583 if (dm_gpio_is_valid(&config->phy_reset_gpio)) {
584 dm_gpio_set_value(&config->phy_reset_gpio, 0);
586 dm_gpio_set_value(&config->phy_reset_gpio, 1);
589 /* Reset the usb controller */
590 clock_enable(config->periph_id);
591 usbf_reset_controller(config, usbctlr);
593 /* enable pinmux bypass */
594 setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
595 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
597 /* Select ULPI parallel interface */
598 init_phy_mux(config, PTS_ULPI, init);
600 /* enable ULPI transceiver */
601 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
603 /* configure ULPI transceiver timings */
605 writel(val, &usbctlr->ulpi_timing_ctrl_1);
607 val |= ULPI_DATA_TRIMMER_SEL(4);
608 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
609 val |= ULPI_DIR_TRIMMER_SEL(4);
610 writel(val, &usbctlr->ulpi_timing_ctrl_1);
613 val |= ULPI_DATA_TRIMMER_LOAD;
614 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
615 val |= ULPI_DIR_TRIMMER_LOAD;
616 writel(val, &usbctlr->ulpi_timing_ctrl_1);
618 /* set up phy for host operation with external vbus supply */
619 ulpi_vp.port_num = 0;
620 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport;
622 if (ulpi_init(&ulpi_vp)) {
623 printf("Tegra ULPI viewport init failed\n");
627 ulpi_set_vbus(&ulpi_vp, 1, 1);
628 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0);
630 /* enable wakeup events */
631 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC);
633 /* Enable and wait for the phy clock to become valid in 100 ms */
634 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
635 for (loop_count = 100000; loop_count != 0; loop_count--) {
636 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
642 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
647 static int init_ulpi_usb_controller(struct fdt_usb *config,
648 enum usb_init_type init)
650 printf("No code to set up ULPI controller, please enable"
651 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT");
656 static void config_clock(const u32 timing[])
658 clock_start_pll(CLOCK_ID_USB,
659 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
660 timing[PARAM_CPCON], timing[PARAM_LFCON]);
663 static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config)
665 const char *phy, *mode;
667 config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
668 mode = fdt_getprop(blob, node, "dr_mode", NULL);
670 if (0 == strcmp(mode, "host"))
671 config->dr_mode = DR_MODE_HOST;
672 else if (0 == strcmp(mode, "peripheral"))
673 config->dr_mode = DR_MODE_DEVICE;
674 else if (0 == strcmp(mode, "otg"))
675 config->dr_mode = DR_MODE_OTG;
677 debug("%s: Cannot decode dr_mode '%s'\n", __func__,
679 return -FDT_ERR_NOTFOUND;
682 config->dr_mode = DR_MODE_HOST;
685 phy = fdt_getprop(blob, node, "phy_type", NULL);
686 config->utmi = phy && 0 == strcmp("utmi", phy);
687 config->ulpi = phy && 0 == strcmp("ulpi", phy);
688 config->enabled = fdtdec_get_is_enabled(blob, node);
689 config->has_legacy_mode = fdtdec_get_bool(blob, node,
690 "nvidia,has-legacy-mode");
691 if (config->has_legacy_mode)
692 port_addr_clear_csc = (unsigned long)config->reg;
693 config->periph_id = clock_decode_periph_id(blob, node);
694 if (config->periph_id == PERIPH_ID_NONE) {
695 debug("%s: Missing/invalid peripheral ID\n", __func__);
696 return -FDT_ERR_NOTFOUND;
698 gpio_request_by_name_nodev(blob, node, "nvidia,vbus-gpio", 0,
699 &config->vbus_gpio, GPIOD_IS_OUT);
700 gpio_request_by_name_nodev(blob, node, "nvidia,phy-reset-gpio", 0,
701 &config->phy_reset_gpio, GPIOD_IS_OUT);
702 debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, "
703 "vbus=%d, phy_reset=%d, dr_mode=%d\n",
704 config->enabled, config->has_legacy_mode, config->utmi,
705 config->ulpi, config->periph_id,
706 gpio_get_number(&config->vbus_gpio),
707 gpio_get_number(&config->phy_reset_gpio), config->dr_mode);
713 * process_usb_nodes() - Process a list of USB nodes, adding them to our list
716 * @node_list: list of nodes to process (any <=0 are ignored)
717 * @count: number of nodes to process
718 * @id: controller type (enum usb_ctlr_type)
720 * Return: 0 - ok, -1 - error
722 static int process_usb_nodes(const void *blob, int node_list[], int count,
723 enum usb_ctlr_type id)
725 struct fdt_usb config;
730 for (i = 0; i < count; i++) {
731 if (port_count == USB_PORTS_MAX) {
732 printf("tegrausb: Cannot register more than %d ports\n",
737 debug("USB %d: ", i);
741 if (fdt_decode_usb(blob, node, &config)) {
742 debug("Cannot decode USB node %s\n",
743 fdt_get_name(blob, node, NULL));
747 config_clock(get_pll_timing(
748 &fdt_usb_controllers[id]));
752 config.initialized = 0;
754 /* add new USB port to the list of available ports */
755 port[port_count++] = config;
761 int usb_process_devicetree(const void *blob)
763 int node_list[USB_PORTS_MAX];
767 for (i = 0; i < ARRAY_SIZE(fdt_usb_controllers); i++) {
768 controller = &fdt_usb_controllers[i];
770 count = fdtdec_find_aliases_for_id(blob, "usb",
771 controller->compat, node_list, USB_PORTS_MAX);
773 err = process_usb_nodes(blob, node_list, count, i);
775 printf("%s: Error processing USB node!\n",
780 if (i == ARRAY_SIZE(fdt_usb_controllers))
787 * Start up the given port number (ports are numbered from 0 on each board).
788 * This returns values for the appropriate hccr and hcor addresses to use for
789 * USB EHCI operations.
791 * @param index port number to start
792 * @param hccr returns start address of EHCI HCCR registers
793 * @param hcor returns start address of EHCI HCOR registers
794 * @return 0 if ok, -1 on error (generally invalid port number)
796 int ehci_hcd_init(int index, enum usb_init_type init,
797 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
799 struct fdt_usb *config;
800 struct usb_ctlr *usbctlr;
802 if (index >= port_count)
805 config = &port[index];
806 ehci_set_controller_priv(index, config);
810 switch (config->dr_mode) {
815 printf("tegrausb: Invalid dr_mode %d for host mode\n",
820 case USB_INIT_DEVICE:
821 if (config->periph_id != PERIPH_ID_USBD) {
822 printf("tegrausb: Device mode only supported on first USB controller\n");
826 printf("tegrausb: Device mode only supported with UTMI PHY\n");
829 switch (config->dr_mode) {
834 printf("tegrausb: Invalid dr_mode %d for device mode\n",
840 printf("tegrausb: Unknown USB_INIT_* %d\n", init);
844 /* skip init, if the port is already initialized */
845 if (config->initialized && config->init_type == init)
848 if (config->utmi && init_utmi_usb_controller(config, init)) {
849 printf("tegrausb: Cannot init port %d\n", index);
853 if (config->ulpi && init_ulpi_usb_controller(config, init)) {
854 printf("tegrausb: Cannot init port %d\n", index);
858 set_up_vbus(config, init);
860 config->initialized = 1;
861 config->init_type = init;
864 usbctlr = config->reg;
865 *hccr = (struct ehci_hccr *)&usbctlr->cap_length;
866 *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd;
872 * Bring down the specified USB controller
874 int ehci_hcd_stop(int index)
876 struct usb_ctlr *usbctlr;
878 usbctlr = port[index].reg;
880 /* Stop controller */
881 writel(0, &usbctlr->usb_cmd);
884 /* Initiate controller reset */
885 writel(2, &usbctlr->usb_cmd);
888 port[index].initialized = 0;