2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * DWC3 controller driver
6 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
8 * SPDX-License-Identifier: GPL-2.0+
17 #include <linux/usb/dwc3.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
23 clrsetbits_le32(&dwc3_reg->g_ctl,
24 DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
25 DWC3_GCTL_PRTCAPDIR(mode));
28 static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
30 /* Assert USB3 PHY reset */
31 setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
33 /* Assert USB2 PHY reset */
34 setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
38 /* Clear USB3 PHY reset */
39 clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
41 /* Clear USB2 PHY reset */
42 clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
45 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
47 /* Before Resetting PHY, put Core in Reset */
48 setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
50 /* reset USB3 phy - if required */
51 dwc3_phy_reset(dwc3_reg);
55 /* After PHYs are stable we can take Core out of reset state */
56 clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
59 int dwc3_core_init(struct dwc3 *dwc3_reg)
63 unsigned int dwc3_hwparams1;
65 revision = readl(&dwc3_reg->g_snpsid);
66 /* This should read as U3 followed by revision number */
67 if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
68 puts("this is not a DesignWare USB3 DRD Core\n");
72 dwc3_core_soft_reset(dwc3_reg);
74 dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
76 reg = readl(&dwc3_reg->g_ctl);
77 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
78 reg &= ~DWC3_GCTL_DISSCRAMBLE;
79 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
80 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
81 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
84 debug("No power optimization available\n");
88 * WORKAROUND: DWC3 revisions <1.90a have a bug
89 * where the device can fail to connect at SuperSpeed
90 * and falls back to high-speed mode which causes
91 * the device to enter a Connect/Disconnect loop
93 if ((revision & DWC3_REVISION_MASK) < 0x190a)
94 reg |= DWC3_GCTL_U2RSTECN;
96 writel(reg, &dwc3_reg->g_ctl);
101 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
103 setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
107 static int xhci_dwc3_probe(struct udevice *dev)
109 struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
110 struct xhci_hcor *hcor;
111 struct xhci_hccr *hccr;
112 struct dwc3 *dwc3_reg;
114 hccr = (struct xhci_hccr *)devfdt_get_addr(dev);
115 hcor = (struct xhci_hcor *)((phys_addr_t)hccr +
116 HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
118 dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
120 dwc3_core_init(dwc3_reg);
122 return xhci_register(dev, hccr, hcor);
125 static int xhci_dwc3_remove(struct udevice *dev)
127 return xhci_deregister(dev);
130 static const struct udevice_id xhci_dwc3_ids[] = {
131 { .compatible = "snps,dwc3" },
135 U_BOOT_DRIVER(xhci_dwc3) = {
138 .of_match = xhci_dwc3_ids,
139 .probe = xhci_dwc3_probe,
140 .remove = xhci_dwc3_remove,
141 .ops = &xhci_usb_ops,
142 .priv_auto_alloc_size = sizeof(struct xhci_ctrl),
143 .platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata),
144 .flags = DM_FLAG_ALLOC_PRIV_DMA,