2 * Mentor USB OTG Core host controller driver.
4 * Copyright (c) 2008 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
27 /* MSC control transfers */
28 #define USB_MSC_BBB_RESET 0xFF
29 #define USB_MSC_BBB_GET_MAX_LUN 0xFE
31 /* Endpoint configuration information */
32 static struct musb_epinfo epinfo[3] = {
33 {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */
34 {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */
35 {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */
39 * This function writes the data toggle value.
41 static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out)
43 u16 toggle = usb_gettoggle(dev, ep, dir_out);
48 writew(MUSB_TXCSR_CLRDATATOG, &musbr->txcsr);
50 csr = readw(&musbr->txcsr);
51 csr |= MUSB_TXCSR_H_WR_DATATOGGLE;
52 writew(csr, &musbr->txcsr);
53 csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT);
54 writew(csr, &musbr->txcsr);
58 writew(MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr);
60 csr = readw(&musbr->rxcsr);
61 csr |= MUSB_RXCSR_H_WR_DATATOGGLE;
62 writew(csr, &musbr->rxcsr);
63 csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE);
64 writew(csr, &musbr->rxcsr);
70 * This function checks if RxStall has occured on the endpoint. If a RxStall
71 * has occured, the RxStall is cleared and 1 is returned. If RxStall has
72 * not occured, 0 is returned.
74 static u8 check_stall(u8 ep, u8 dir_out)
80 csr = readw(&musbr->txcsr);
81 if (csr & MUSB_CSR0_H_RXSTALL) {
82 csr &= ~MUSB_CSR0_H_RXSTALL;
83 writew(csr, &musbr->txcsr);
86 } else { /* For non-ep0 */
87 if (dir_out) { /* is it tx ep */
88 csr = readw(&musbr->txcsr);
89 if (csr & MUSB_TXCSR_H_RXSTALL) {
90 csr &= ~MUSB_TXCSR_H_RXSTALL;
91 writew(csr, &musbr->txcsr);
94 } else { /* is it rx ep */
95 csr = readw(&musbr->rxcsr);
96 if (csr & MUSB_RXCSR_H_RXSTALL) {
97 csr &= ~MUSB_RXCSR_H_RXSTALL;
98 writew(csr, &musbr->rxcsr);
107 * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout
108 * error and -2 for stall.
110 static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
114 int timeout = CONFIG_MUSB_TIMEOUT;
117 csr = readw(&musbr->txcsr);
118 if (csr & MUSB_CSR0_H_ERROR) {
119 csr &= ~MUSB_CSR0_H_ERROR;
120 writew(csr, &musbr->txcsr);
121 dev->status = USB_ST_CRC_ERR;
127 case MUSB_CSR0_TXPKTRDY:
128 if (!(csr & MUSB_CSR0_TXPKTRDY)) {
129 if (check_stall(MUSB_CONTROL_EP, 0)) {
130 dev->status = USB_ST_STALLED;
137 case MUSB_CSR0_RXPKTRDY:
138 if (check_stall(MUSB_CONTROL_EP, 0)) {
139 dev->status = USB_ST_STALLED;
142 if (csr & MUSB_CSR0_RXPKTRDY)
146 case MUSB_CSR0_H_REQPKT:
147 if (!(csr & MUSB_CSR0_H_REQPKT)) {
148 if (check_stall(MUSB_CONTROL_EP, 0)) {
149 dev->status = USB_ST_STALLED;
157 /* Check the timeout */
161 dev->status = USB_ST_CRC_ERR;
171 * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error.
173 static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep)
176 int timeout = CONFIG_MUSB_TIMEOUT;
179 if (check_stall(ep, 1)) {
180 dev->status = USB_ST_STALLED;
184 csr = readw(&musbr->txcsr);
185 if (csr & MUSB_TXCSR_H_ERROR) {
186 dev->status = USB_ST_CRC_ERR;
190 /* Check the timeout */
194 dev->status = USB_ST_CRC_ERR;
198 } while (csr & MUSB_TXCSR_TXPKTRDY);
203 * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error.
205 static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep)
208 int timeout = CONFIG_MUSB_TIMEOUT;
211 if (check_stall(ep, 0)) {
212 dev->status = USB_ST_STALLED;
216 csr = readw(&musbr->rxcsr);
217 if (csr & MUSB_RXCSR_H_ERROR) {
218 dev->status = USB_ST_CRC_ERR;
222 /* Check the timeout */
226 dev->status = USB_ST_CRC_ERR;
230 } while (!(csr & MUSB_RXCSR_RXPKTRDY));
235 * This function performs the setup phase of the control transfer
237 static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup)
242 /* write the control request to ep0 fifo */
243 write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup);
245 /* enable transfer of setup packet */
246 csr = readw(&musbr->txcsr);
247 csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT);
248 writew(csr, &musbr->txcsr);
250 /* wait until the setup packet is transmitted */
251 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
257 * This function handles the control transfer in data phase
259 static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer)
264 u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
265 u8 *rxbuff = (u8 *)buffer;
269 while (rxlen < len) {
270 /* Determine the next read length */
271 nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen);
273 /* Set the ReqPkt bit */
274 csr = readw(&musbr->txcsr);
275 writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr);
276 result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY);
280 /* Actual number of bytes received by usb */
281 rxedlength = readb(&musbr->rxcount);
283 /* Read the data from the RxFIFO */
284 read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]);
286 /* Clear the RxPktRdy Bit */
287 csr = readw(&musbr->txcsr);
288 csr &= ~MUSB_CSR0_RXPKTRDY;
289 writew(csr, &musbr->txcsr);
292 if (rxedlength != nextlen) {
293 dev->act_len += rxedlength;
297 dev->act_len = rxlen;
303 * This function handles the control transfer out data phase
305 static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer)
310 u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
311 u8 *txbuff = (u8 *)buffer;
314 while (txlen < len) {
315 /* Determine the next write length */
316 nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen);
318 /* Load the data to send in FIFO */
319 write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]);
321 /* Set TXPKTRDY bit */
322 csr = readw(&musbr->txcsr);
323 writew(csr | MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY,
325 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
330 dev->act_len = txlen;
336 * This function handles the control transfer out status phase
338 static int ctrlreq_out_status_phase(struct usb_device *dev)
343 /* Set the StatusPkt bit */
344 csr = readw(&musbr->txcsr);
345 csr |= (MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY |
346 MUSB_CSR0_H_STATUSPKT);
347 writew(csr, &musbr->txcsr);
349 /* Wait until TXPKTRDY bit is cleared */
350 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
355 * This function handles the control transfer in status phase
357 static int ctrlreq_in_status_phase(struct usb_device *dev)
362 /* Set the StatusPkt bit and ReqPkt bit */
363 csr = MUSB_CSR0_H_DIS_PING | MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT;
364 writew(csr, &musbr->txcsr);
365 result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT);
367 /* clear StatusPkt bit and RxPktRdy bit */
368 csr = readw(&musbr->txcsr);
369 csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT);
370 writew(csr, &musbr->txcsr);
375 * determines the speed of the device (High/Full/Slow)
377 static u8 get_dev_speed(struct usb_device *dev)
379 return (dev->speed & USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH :
380 ((dev->speed & USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW :
381 MUSB_TYPE_SPEED_FULL);
385 * configure the hub address and the port address.
387 static void config_hub_port(struct usb_device *dev, u8 ep)
392 /* Find out the nearest parent which is high speed */
393 while (dev->parent->parent != NULL)
394 if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH)
399 /* determine the port address at that hub */
400 hub = dev->parent->devnum;
401 for (chid = 0; chid < USB_MAXCHILDREN; chid++)
402 if (dev->parent->children[chid] == dev)
405 /* configure the hub address and the port address */
406 writeb(hub, &musbr->tar[ep].txhubaddr);
407 writeb((chid + 1), &musbr->tar[ep].txhubport);
408 writeb(hub, &musbr->tar[ep].rxhubaddr);
409 writeb((chid + 1), &musbr->tar[ep].rxhubport);
413 * do a control transfer
415 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
416 int len, struct devrequest *setup)
418 int devnum = usb_pipedevice(pipe);
422 /* select control endpoint */
423 writeb(MUSB_CONTROL_EP, &musbr->index);
424 csr = readw(&musbr->txcsr);
426 /* target addr and (for multipoint) hub addr/port */
427 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr);
428 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr);
430 /* configure the hub address and the port number as required */
431 devspeed = get_dev_speed(dev);
432 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
433 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
434 config_hub_port(dev, MUSB_CONTROL_EP);
435 writeb(devspeed << 6, &musbr->txtype);
437 writeb(musb_cfg.musb_speed << 6, &musbr->txtype);
438 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr);
439 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport);
440 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr);
441 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport);
444 /* Control transfer setup phase */
445 if (ctrlreq_setup_phase(dev, setup) < 0)
448 switch (setup->request) {
449 case USB_REQ_GET_DESCRIPTOR:
450 case USB_REQ_GET_CONFIGURATION:
451 case USB_REQ_GET_INTERFACE:
452 case USB_REQ_GET_STATUS:
453 case USB_MSC_BBB_GET_MAX_LUN:
454 /* control transfer in-data-phase */
455 if (ctrlreq_in_data_phase(dev, len, buffer) < 0)
457 /* control transfer out-status-phase */
458 if (ctrlreq_out_status_phase(dev) < 0)
462 case USB_REQ_SET_ADDRESS:
463 case USB_REQ_SET_CONFIGURATION:
464 case USB_REQ_SET_FEATURE:
465 case USB_REQ_SET_INTERFACE:
466 case USB_REQ_CLEAR_FEATURE:
467 case USB_MSC_BBB_RESET:
468 /* control transfer in status phase */
469 if (ctrlreq_in_status_phase(dev) < 0)
473 case USB_REQ_SET_DESCRIPTOR:
474 /* control transfer out data phase */
475 if (ctrlreq_out_data_phase(dev, len, buffer) < 0)
477 /* control transfer in status phase */
478 if (ctrlreq_in_status_phase(dev) < 0)
483 /* unhandled control transfer */
495 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
496 void *buffer, int len)
498 int dir_out = usb_pipeout(pipe);
499 int ep = usb_pipeendpoint(pipe);
500 int devnum = usb_pipedevice(pipe);
507 /* select bulk endpoint */
508 writeb(MUSB_BULK_EP, &musbr->index);
510 /* write the address of the device */
512 writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr);
514 writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr);
516 /* configure the hub address and the port number as required */
517 devspeed = get_dev_speed(dev);
518 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
519 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
521 * MUSB is in high speed and the destination device is full
522 * speed device. So configure the hub address and port
525 config_hub_port(dev, MUSB_BULK_EP);
528 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr);
529 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport);
531 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr);
532 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport);
534 devspeed = musb_cfg.musb_speed;
537 /* Write the saved toggle bit value */
538 write_toggle(dev, ep, dir_out);
540 if (dir_out) { /* bulk-out transfer */
541 /* Program the TxType register */
542 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
543 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
544 (ep & MUSB_TYPE_REMOTE_END);
545 writeb(type, &musbr->txtype);
547 /* Write maximum packet size to the TxMaxp register */
548 writew(dev->epmaxpacketout[ep], &musbr->txmaxp);
549 while (txlen < len) {
550 nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ?
551 (len-txlen) : dev->epmaxpacketout[ep];
553 /* Write the data to the FIFO */
554 write_fifo(MUSB_BULK_EP, nextlen,
555 (void *)(((u8 *)buffer) + txlen));
557 /* Set the TxPktRdy bit */
558 csr = readw(&musbr->txcsr);
559 writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr);
561 /* Wait until the TxPktRdy bit is cleared */
562 if (!wait_until_txep_ready(dev, MUSB_BULK_EP)) {
563 readw(&musbr->txcsr);
564 usb_settoggle(dev, ep, dir_out,
565 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
566 dev->act_len = txlen;
572 /* Keep a copy of the data toggle bit */
573 csr = readw(&musbr->txcsr);
574 usb_settoggle(dev, ep, dir_out,
575 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
576 } else { /* bulk-in transfer */
577 /* Write the saved toggle bit value */
578 write_toggle(dev, ep, dir_out);
580 /* Program the RxType register */
581 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
582 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
583 (ep & MUSB_TYPE_REMOTE_END);
584 writeb(type, &musbr->rxtype);
586 /* Write the maximum packet size to the RxMaxp register */
587 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
588 while (txlen < len) {
589 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
590 (len-txlen) : dev->epmaxpacketin[ep];
592 /* Set the ReqPkt bit */
593 writew(MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
595 /* Wait until the RxPktRdy bit is set */
596 if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) {
597 csr = readw(&musbr->rxcsr);
598 usb_settoggle(dev, ep, dir_out,
599 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
600 csr &= ~MUSB_RXCSR_RXPKTRDY;
601 writew(csr, &musbr->rxcsr);
602 dev->act_len = txlen;
606 /* Read the data from the FIFO */
607 read_fifo(MUSB_BULK_EP, nextlen,
608 (void *)(((u8 *)buffer) + txlen));
610 /* Clear the RxPktRdy bit */
611 csr = readw(&musbr->rxcsr);
612 csr &= ~MUSB_RXCSR_RXPKTRDY;
613 writew(csr, &musbr->rxcsr);
617 /* Keep a copy of the data toggle bit */
618 csr = readw(&musbr->rxcsr);
619 usb_settoggle(dev, ep, dir_out,
620 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
623 /* bulk transfer is complete */
630 * This function initializes the usb controller module.
632 int usb_lowlevel_init(void)
637 if (musb_platform_init() == -1)
640 /* Configure all the endpoint FIFO's and start usb controller */
641 musbr = musb_cfg.regs;
642 musb_configure_ep(&epinfo[0],
643 sizeof(epinfo) / sizeof(struct musb_epinfo));
647 * Wait until musb is enabled in host mode with a timeout. There
648 * should be a usb device connected.
650 timeout = musb_cfg.timeout;
652 if (readb(&musbr->devctl) & MUSB_DEVCTL_HM)
655 /* if musb core is not in host mode, then return */
659 /* start usb bus reset */
660 power = readb(&musbr->power);
661 writeb(power | MUSB_POWER_RESET, &musbr->power);
663 /* After initiating a usb reset, wait for about 20ms to 30ms */
666 /* stop usb bus reset */
667 power = readb(&musbr->power);
668 power &= ~MUSB_POWER_RESET;
669 writeb(power, &musbr->power);
671 /* Determine if the connected device is a high/full/low speed device */
672 musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ?
673 MUSB_TYPE_SPEED_HIGH :
674 ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ?
675 MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW);
680 * This function stops the operation of the davinci usb module.
682 int usb_lowlevel_stop(void)
684 /* Reset the USB module */
685 musb_platform_deinit();
686 writeb(0, &musbr->devctl);
691 * This function supports usb interrupt transfers. Currently, usb interrupt
692 * transfers are not supported.
694 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
695 void *buffer, int len, int interval)
697 int dir_out = usb_pipeout(pipe);
698 int ep = usb_pipeendpoint(pipe);
699 int devnum = usb_pipedevice(pipe);
706 /* select interrupt endpoint */
707 writeb(MUSB_INTR_EP, &musbr->index);
709 /* write the address of the device */
711 writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr);
713 writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr);
715 /* configure the hub address and the port number as required */
716 devspeed = get_dev_speed(dev);
717 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
718 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
720 * MUSB is in high speed and the destination device is full
721 * speed device. So configure the hub address and port
724 config_hub_port(dev, MUSB_INTR_EP);
727 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr);
728 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport);
730 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr);
731 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport);
733 devspeed = musb_cfg.musb_speed;
736 /* Write the saved toggle bit value */
737 write_toggle(dev, ep, dir_out);
739 if (!dir_out) { /* intrrupt-in transfer */
740 /* Write the saved toggle bit value */
741 write_toggle(dev, ep, dir_out);
742 writeb(interval, &musbr->rxinterval);
744 /* Program the RxType register */
745 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
746 (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) |
747 (ep & MUSB_TYPE_REMOTE_END);
748 writeb(type, &musbr->rxtype);
750 /* Write the maximum packet size to the RxMaxp register */
751 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
753 while (txlen < len) {
754 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
755 (len-txlen) : dev->epmaxpacketin[ep];
757 /* Set the ReqPkt bit */
758 writew(MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
760 /* Wait until the RxPktRdy bit is set */
761 if (!wait_until_rxep_ready(dev, MUSB_INTR_EP)) {
762 csr = readw(&musbr->rxcsr);
763 usb_settoggle(dev, ep, dir_out,
764 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
765 csr &= ~MUSB_RXCSR_RXPKTRDY;
766 writew(csr, &musbr->rxcsr);
767 dev->act_len = txlen;
771 /* Read the data from the FIFO */
772 read_fifo(MUSB_INTR_EP, nextlen,
773 (void *)(((u8 *)buffer) + txlen));
775 /* Clear the RxPktRdy bit */
776 csr = readw(&musbr->rxcsr);
777 csr &= ~MUSB_RXCSR_RXPKTRDY;
778 writew(csr, &musbr->rxcsr);
782 /* Keep a copy of the data toggle bit */
783 csr = readw(&musbr->rxcsr);
784 usb_settoggle(dev, ep, dir_out,
785 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
788 /* interrupt transfer is complete */
790 dev->irq_act_len = len;
791 dev->irq_handle(dev);
798 #ifdef CONFIG_SYS_USB_EVENT_POLL
800 * This function polls for USB keyboard data.
802 void usb_event_poll()
805 struct usb_device *usb_kbd_dev;
806 struct usb_interface_descriptor *iface;
807 struct usb_endpoint_descriptor *ep;
811 /* Get the pointer to USB Keyboard device pointer */
812 dev = device_get_by_name("usbkbd");
813 usb_kbd_dev = (struct usb_device *)dev->priv;
814 iface = &usb_kbd_dev->config.if_desc[0];
815 ep = &iface->ep_desc[0];
816 pipe = usb_rcvintpipe(usb_kbd_dev, ep->bEndpointAddress);
818 /* Submit a interrupt transfer request */
819 maxp = usb_maxpacket(usb_kbd_dev, pipe);
820 usb_submit_int_msg(usb_kbd_dev, pipe, &new[0],
821 maxp > 8 ? 8 : maxp, ep->bInterval);
823 #endif /* CONFIG_SYS_USB_EVENT_POLL */