1 // SPDX-License-Identifier: GPL-2.0
3 * Allwinner SUNXI "glue layer"
5 * Copyright © 2015 Hans de Goede <hdegoede@redhat.com>
6 * Copyright © 2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
8 * Based on the sw_usb "Allwinner OTG Dual Role Controller" code.
9 * Copyright 2007-2012 (C) Allwinner Technology Co., Ltd.
10 * javen <javen@allwinnertech.com>
12 * Based on the DA8xx "glue layer" code.
13 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
14 * Copyright (C) 2005-2006 by Texas Instruments
16 * This file is part of the Inventra Controller Driver for Linux.
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/usb_phy.h>
24 #include <asm-generic/gpio.h>
27 #include <linux/usb/musb.h>
28 #include "linux-compat.h"
29 #include "musb_core.h"
30 #include "musb_uboot.h"
32 /******************************************************************************
33 ******************************************************************************
34 * From the Allwinner driver
35 ******************************************************************************
36 ******************************************************************************/
38 /******************************************************************************
39 * From include/sunxi_usb_bsp.h
40 ******************************************************************************/
43 #define USBC_REG_o_ISCR 0x0400
44 #define USBC_REG_o_PHYCTL 0x0404
45 #define USBC_REG_o_PHYBIST 0x0408
46 #define USBC_REG_o_PHYTUNE 0x040c
48 #define USBC_REG_o_VEND0 0x0043
50 /* Interface Status and Control */
51 #define USBC_BP_ISCR_VBUS_VALID_FROM_DATA 30
52 #define USBC_BP_ISCR_VBUS_VALID_FROM_VBUS 29
53 #define USBC_BP_ISCR_EXT_ID_STATUS 28
54 #define USBC_BP_ISCR_EXT_DM_STATUS 27
55 #define USBC_BP_ISCR_EXT_DP_STATUS 26
56 #define USBC_BP_ISCR_MERGED_VBUS_STATUS 25
57 #define USBC_BP_ISCR_MERGED_ID_STATUS 24
59 #define USBC_BP_ISCR_ID_PULLUP_EN 17
60 #define USBC_BP_ISCR_DPDM_PULLUP_EN 16
61 #define USBC_BP_ISCR_FORCE_ID 14
62 #define USBC_BP_ISCR_FORCE_VBUS_VALID 12
63 #define USBC_BP_ISCR_VBUS_VALID_SRC 10
65 #define USBC_BP_ISCR_HOSC_EN 7
66 #define USBC_BP_ISCR_VBUS_CHANGE_DETECT 6
67 #define USBC_BP_ISCR_ID_CHANGE_DETECT 5
68 #define USBC_BP_ISCR_DPDM_CHANGE_DETECT 4
69 #define USBC_BP_ISCR_IRQ_ENABLE 3
70 #define USBC_BP_ISCR_VBUS_CHANGE_DETECT_EN 2
71 #define USBC_BP_ISCR_ID_CHANGE_DETECT_EN 1
72 #define USBC_BP_ISCR_DPDM_CHANGE_DETECT_EN 0
74 /******************************************************************************
76 ******************************************************************************/
79 struct musb_host_data mdata;
80 struct sunxi_ccm_reg *ccm;
83 #define to_sunxi_glue(d) container_of(d, struct sunxi_glue, dev)
85 static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val)
89 temp &= ~(1 << USBC_BP_ISCR_VBUS_CHANGE_DETECT);
90 temp &= ~(1 << USBC_BP_ISCR_ID_CHANGE_DETECT);
91 temp &= ~(1 << USBC_BP_ISCR_DPDM_CHANGE_DETECT);
96 static void USBC_EnableIdPullUp(__iomem void *base)
100 reg_val = musb_readl(base, USBC_REG_o_ISCR);
101 reg_val |= (1 << USBC_BP_ISCR_ID_PULLUP_EN);
102 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
103 musb_writel(base, USBC_REG_o_ISCR, reg_val);
106 static void USBC_EnableDpDmPullUp(__iomem void *base)
110 reg_val = musb_readl(base, USBC_REG_o_ISCR);
111 reg_val |= (1 << USBC_BP_ISCR_DPDM_PULLUP_EN);
112 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
113 musb_writel(base, USBC_REG_o_ISCR, reg_val);
116 static void USBC_ForceIdToLow(__iomem void *base)
120 reg_val = musb_readl(base, USBC_REG_o_ISCR);
121 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
122 reg_val |= (0x02 << USBC_BP_ISCR_FORCE_ID);
123 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
124 musb_writel(base, USBC_REG_o_ISCR, reg_val);
127 static void USBC_ForceIdToHigh(__iomem void *base)
131 reg_val = musb_readl(base, USBC_REG_o_ISCR);
132 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
133 reg_val |= (0x03 << USBC_BP_ISCR_FORCE_ID);
134 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
135 musb_writel(base, USBC_REG_o_ISCR, reg_val);
138 static void USBC_ForceVbusValidToLow(__iomem void *base)
142 reg_val = musb_readl(base, USBC_REG_o_ISCR);
143 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
144 reg_val |= (0x02 << USBC_BP_ISCR_FORCE_VBUS_VALID);
145 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
146 musb_writel(base, USBC_REG_o_ISCR, reg_val);
149 static void USBC_ForceVbusValidToHigh(__iomem void *base)
153 reg_val = musb_readl(base, USBC_REG_o_ISCR);
154 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
155 reg_val |= (0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
156 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
157 musb_writel(base, USBC_REG_o_ISCR, reg_val);
160 static void USBC_ConfigFIFO_Base(void)
164 /* config usb fifo, 8kb mode */
165 reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
166 reg_value &= ~(0x03 << 0);
167 reg_value |= (1 << 0);
168 writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
171 /******************************************************************************
172 * Needed for the DFU polling magic
173 ******************************************************************************/
175 static u8 last_int_usb;
177 bool dfu_usb_get_reset(void)
179 return !!(last_int_usb & MUSB_INTR_RESET);
182 /******************************************************************************
184 ******************************************************************************/
186 static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
188 struct musb *musb = __hci;
189 irqreturn_t retval = IRQ_NONE;
191 /* read and flush interrupts */
192 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
193 last_int_usb = musb->int_usb;
195 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
196 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
198 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
199 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
201 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
203 if (musb->int_usb || musb->int_tx || musb->int_rx)
204 retval |= musb_interrupt(musb);
209 /* musb_core does not call enable / disable in a balanced manner <sigh> */
210 static bool enabled = false;
212 static int sunxi_musb_enable(struct musb *musb)
216 pr_debug("%s():\n", __func__);
218 musb_ep_select(musb->mregs, 0);
219 musb_writeb(musb->mregs, MUSB_FADDR, 0);
224 /* select PIO mode */
225 musb_writeb(musb->mregs, USBC_REG_o_VEND0, 0);
227 if (is_host_enabled(musb)) {
228 ret = sunxi_usb_phy_vbus_detect(0);
230 printf("A charger is plugged into the OTG: ");
233 ret = sunxi_usb_phy_id_detect(0);
235 printf("No host cable detected: ");
238 sunxi_usb_phy_power_on(0); /* port power on */
241 USBC_ForceVbusValidToHigh(musb->mregs);
247 static void sunxi_musb_disable(struct musb *musb)
249 pr_debug("%s():\n", __func__);
254 if (is_host_enabled(musb))
255 sunxi_usb_phy_power_off(0); /* port power off */
257 USBC_ForceVbusValidToLow(musb->mregs);
258 mdelay(200); /* Wait for the current session to timeout */
263 static int sunxi_musb_init(struct musb *musb)
265 struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
267 pr_debug("%s():\n", __func__);
269 musb->isr = sunxi_musb_interrupt;
271 setbits_le32(&glue->ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
272 #ifdef CONFIG_SUNXI_GEN_SUN6I
273 setbits_le32(&glue->ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
275 sunxi_usb_phy_init(0);
277 USBC_ConfigFIFO_Base();
278 USBC_EnableDpDmPullUp(musb->mregs);
279 USBC_EnableIdPullUp(musb->mregs);
281 if (is_host_enabled(musb)) {
283 USBC_ForceIdToLow(musb->mregs);
285 /* Peripheral mode */
286 USBC_ForceIdToHigh(musb->mregs);
288 USBC_ForceVbusValidToHigh(musb->mregs);
293 static const struct musb_platform_ops sunxi_musb_ops = {
294 .init = sunxi_musb_init,
295 .enable = sunxi_musb_enable,
296 .disable = sunxi_musb_disable,
299 /* Allwinner OTG supports up to 5 endpoints */
300 #define SUNXI_MUSB_MAX_EP_NUM 6
301 #define SUNXI_MUSB_RAM_BITS 11
303 static struct musb_hdrc_config musb_config = {
306 .num_eps = SUNXI_MUSB_MAX_EP_NUM,
307 .ram_bits = SUNXI_MUSB_RAM_BITS,
310 static struct musb_hdrc_platform_data musb_plat = {
311 #if defined(CONFIG_USB_MUSB_HOST)
314 .mode = MUSB_PERIPHERAL,
316 .config = &musb_config,
318 .platform_ops = &sunxi_musb_ops,
321 static int musb_usb_probe(struct udevice *dev)
323 struct sunxi_glue *glue = dev_get_priv(dev);
324 struct musb_host_data *host = &glue->mdata;
325 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
326 void *base = dev_read_addr_ptr(dev);
332 glue->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
333 if (IS_ERR(glue->ccm))
334 return PTR_ERR(glue->ccm);
336 priv->desc_before_addr = true;
338 #ifdef CONFIG_USB_MUSB_HOST
339 host->host = musb_init_controller(&musb_plat, &glue->dev, base);
343 ret = musb_lowlevel_init(host);
345 printf("Allwinner mUSB OTG (Host)\n");
347 ret = musb_register(&musb_plat, &glue->dev, base);
349 printf("Allwinner mUSB OTG (Peripheral)\n");
355 static int musb_usb_remove(struct udevice *dev)
357 struct sunxi_glue *glue = dev_get_priv(dev);
358 struct musb_host_data *host = &glue->mdata;
360 musb_stop(host->host);
362 sunxi_usb_phy_exit(0);
363 #ifdef CONFIG_SUNXI_GEN_SUN6I
364 clrbits_le32(&glue->ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
366 clrbits_le32(&glue->ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
374 static const struct udevice_id sunxi_musb_ids[] = {
375 { .compatible = "allwinner,sun4i-a10-musb" },
376 { .compatible = "allwinner,sun6i-a31-musb" },
377 { .compatible = "allwinner,sun8i-a33-musb" },
378 { .compatible = "allwinner,sun8i-h3-musb" },
382 U_BOOT_DRIVER(usb_musb) = {
383 .name = "sunxi-musb",
384 #ifdef CONFIG_USB_MUSB_HOST
387 .id = UCLASS_USB_DEV_GENERIC,
389 .of_match = sunxi_musb_ids,
390 .probe = musb_usb_probe,
391 .remove = musb_usb_remove,
392 #ifdef CONFIG_USB_MUSB_HOST
393 .ops = &musb_usb_ops,
395 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
396 .priv_auto_alloc_size = sizeof(struct sunxi_glue),