git.sur5r.net Git - u-boot/blob - drivers/video/atmel_hlcdfb.c

   1 /*
   2  * Driver for AT91/AT32 MULTI LAYER LCD Controller
   3  *
   4  * Copyright (C) 2012 Atmel Corporation
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/gpio.h>
  28 #include <asm/arch/clk.h>
  29 #include <lcd.h>
  30 #include <atmel_hlcdc.h>
  31
  32 void *lcd_base;                         /* Start of framebuffer memory  */
  33
  34 /* configurable parameters */
  35 #define ATMEL_LCDC_CVAL_DEFAULT         0xc8
  36 #define ATMEL_LCDC_DMA_BURST_LEN        8
  37 #ifndef ATMEL_LCDC_GUARD_TIME
  38 #define ATMEL_LCDC_GUARD_TIME           1
  39 #endif
  40
  41 #define ATMEL_LCDC_FIFO_SIZE            512
  42
  43 #define lcdc_readl(reg)         __raw_readl((reg))
  44 #define lcdc_writel(reg, val)   __raw_writel((val), (reg))
  45
  46 /*
  47  * the CLUT register map as following
  48  * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0)
  49  */
  50 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  51 {
  52         lcdc_writel(((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk)
  53                 | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk)
  54                 | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk),
  55                 panel_info.mmio + ATMEL_LCDC_LUT(regno));
  56 }
  57
  58 void lcd_ctrl_init(void *lcdbase)
  59 {
  60         unsigned long value;
  61         struct lcd_dma_desc *desc;
  62         struct atmel_hlcd_regs *regs;
  63
  64         if (!has_lcdc())
  65                 return;     /* No lcdc */
  66
  67         regs = (struct atmel_hlcd_regs *)panel_info.mmio;
  68
  69         /* Disable DISP signal */
  70         lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_DISPDIS);
  71         while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS))
  72                 udelay(1);
  73         /* Disable synchronization */
  74         lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_SYNCDIS);
  75         while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS))
  76                 udelay(1);
  77         /* Disable pixel clock */
  78         lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_CLKDIS);
  79         while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS))
  80                 udelay(1);
  81         /* Disable PWM */
  82         lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_PWMDIS);
  83         while ((lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
  84                 udelay(1);
  85
  86         /* Set pixel clock */
  87         value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
  88         if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
  89                 value++;
  90
  91         if (value < 1) {
  92                 /* Using system clock as pixel clock */
  93                 lcdc_writel(&regs->lcdc_lcdcfg0,
  94                                         LCDC_LCDCFG0_CLKDIV(0)
  95                                         | LCDC_LCDCFG0_CGDISHCR
  96                                         | LCDC_LCDCFG0_CGDISHEO
  97                                         | LCDC_LCDCFG0_CGDISOVR1
  98                                         | LCDC_LCDCFG0_CGDISBASE
  99                                         | panel_info.vl_clk_pol
 100                                         | LCDC_LCDCFG0_CLKSEL);
 101
 102         } else {
 103                 lcdc_writel(&regs->lcdc_lcdcfg0,
 104                                 LCDC_LCDCFG0_CLKDIV(value - 2)
 105                                 | LCDC_LCDCFG0_CGDISHCR
 106                                 | LCDC_LCDCFG0_CGDISHEO
 107                                 | LCDC_LCDCFG0_CGDISOVR1
 108                                 | LCDC_LCDCFG0_CGDISBASE
 109                                 | panel_info.vl_clk_pol);
 110         }
 111
 112         /* Initialize control register 5 */
 113         value = 0;
 114
 115         value |= panel_info.vl_sync;
 116
 117 #ifndef LCD_OUTPUT_BPP
 118         /* Output is 24bpp */
 119         value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
 120 #else
 121         switch (LCD_OUTPUT_BPP) {
 122         case 12:
 123                 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
 124                 break;
 125         case 16:
 126                 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
 127                 break;
 128         case 18:
 129                 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
 130                 break;
 131         case 24:
 132                 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
 133                 break;
 134         default:
 135                 BUG();
 136                 break;
 137         }
 138 #endif
 139
 140         value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
 141         value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
 142         lcdc_writel(&regs->lcdc_lcdcfg5, value);
 143
 144         /* Vertical & Horizontal Timing */
 145         value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
 146         value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
 147         lcdc_writel(&regs->lcdc_lcdcfg1, value);
 148
 149         value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin);
 150         value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1);
 151         lcdc_writel(&regs->lcdc_lcdcfg2, value);
 152
 153         value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1);
 154         value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1);
 155         lcdc_writel(&regs->lcdc_lcdcfg3, value);
 156
 157         /* Display size */
 158         value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
 159         value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
 160         lcdc_writel(&regs->lcdc_lcdcfg4, value);
 161
 162         lcdc_writel(&regs->lcdc_basecfg0,
 163                         LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO);
 164
 165         switch (NBITS(panel_info.vl_bpix)) {
 166         case 16:
 167                 lcdc_writel(&regs->lcdc_basecfg1,
 168                         LCDC_BASECFG1_RGBMODE_16BPP_RGB_565);
 169                 break;
 170         default:
 171                 BUG();
 172                 break;
 173         }
 174
 175         lcdc_writel(&regs->lcdc_basecfg2, LCDC_BASECFG2_XSTRIDE(0));
 176         lcdc_writel(&regs->lcdc_basecfg3, 0);
 177         lcdc_writel(&regs->lcdc_basecfg4, LCDC_BASECFG4_DMA);
 178
 179         /* Disable all interrupts */
 180         lcdc_writel(&regs->lcdc_lcdidr, ~0UL);
 181         lcdc_writel(&regs->lcdc_baseidr, ~0UL);
 182
 183         /* Setup the DMA descriptor, this descriptor will loop to itself */
 184         desc = (struct lcd_dma_desc *)(lcdbase - 16);
 185
 186         desc->address = (u32)lcdbase;
 187         /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
 188         desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
 189                         | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
 190         desc->next = (u32)desc;
 191
 192         lcdc_writel(&regs->lcdc_baseaddr, desc->address);
 193         lcdc_writel(&regs->lcdc_basectrl, desc->control);
 194         lcdc_writel(&regs->lcdc_basenext, desc->next);
 195         lcdc_writel(&regs->lcdc_basecher, LCDC_BASECHER_CHEN |
 196                                           LCDC_BASECHER_UPDATEEN);
 197
 198         /* Enable LCD */
 199         value = lcdc_readl(&regs->lcdc_lcden);
 200         lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_CLKEN);
 201         while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS))
 202                 udelay(1);
 203         value = lcdc_readl(&regs->lcdc_lcden);
 204         lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_SYNCEN);
 205         while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS))
 206                 udelay(1);
 207         value = lcdc_readl(&regs->lcdc_lcden);
 208         lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_DISPEN);
 209         while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS))
 210                 udelay(1);
 211         value = lcdc_readl(&regs->lcdc_lcden);
 212         lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_PWMEN);
 213         while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
 214                 udelay(1);
 215 }