2 * Driver for AT91/AT32 LCD Controller
4 * Copyright (C) 2007 Atmel Corporation
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/gpio.h>
12 #include <asm/arch/clk.h>
14 #include <atmel_lcdc.h>
16 /* configurable parameters */
17 #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
18 #define ATMEL_LCDC_DMA_BURST_LEN 8
19 #ifndef ATMEL_LCDC_GUARD_TIME
20 #define ATMEL_LCDC_GUARD_TIME 1
23 #if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91CAP9)
24 #define ATMEL_LCDC_FIFO_SIZE 2048
26 #define ATMEL_LCDC_FIFO_SIZE 512
29 #define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg))
30 #define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg))
32 ushort *configuration_get_cmap(void)
34 return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
37 #if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555)
38 void fb_put_word(uchar **fb, uchar **from)
40 *(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03);
41 *(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2);
46 #ifdef CONFIG_LCD_LOGO
48 void lcd_logo_set_cmap(void)
53 uint *cmap = (uint *)configuration_get_cmap();
55 for (i = 0; i < BMP_LOGO_COLORS; ++i) {
56 colreg = bmp_logo_palette[i];
57 #ifdef CONFIG_ATMEL_LCD_BGR555
58 lut_entry = ((colreg & 0x000F) << 11) |
59 ((colreg & 0x00F0) << 2) |
60 ((colreg & 0x0F00) >> 7);
62 lut_entry = ((colreg & 0x000F) << 1) |
63 ((colreg & 0x00F0) << 3) |
64 ((colreg & 0x0F00) << 4);
66 *(cmap + BMP_LOGO_OFFSET) = lut_entry;
72 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
74 #if defined(CONFIG_ATMEL_LCD_BGR555)
75 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
76 (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
78 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
79 (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
83 void lcd_ctrl_init(void *lcdbase)
87 /* Turn off the LCD controller and the DMA controller */
88 lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
89 ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
91 /* Wait for the LCDC core to become idle */
92 while (lcdc_readl(panel_info.mmio, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
95 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, 0);
98 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
100 /* ...set frame size and burst length = 8 words (?) */
101 value = (panel_info.vl_col * panel_info.vl_row *
102 NBITS(panel_info.vl_bpix)) / 32;
103 value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
104 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMAFRMCFG, value);
106 /* Set pixel clock */
107 value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
108 if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
110 value = (value / 2) - 1;
113 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
115 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1,
116 value << ATMEL_LCDC_CLKVAL_OFFSET);
118 /* Initialize control register 2 */
120 value = ATMEL_LCDC_MEMOR_BIG | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
122 value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
124 if (panel_info.vl_tft)
125 value |= ATMEL_LCDC_DISTYPE_TFT;
127 value |= panel_info.vl_sync;
128 value |= (panel_info.vl_bpix << 5);
129 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value);
131 /* Vertical timing */
132 value = (panel_info.vl_vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
133 value |= panel_info.vl_upper_margin << ATMEL_LCDC_VBP_OFFSET;
134 value |= panel_info.vl_lower_margin;
135 lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM1, value);
137 /* Horizontal timing */
138 value = (panel_info.vl_right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
139 value |= (panel_info.vl_hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
140 value |= (panel_info.vl_left_margin - 1);
141 lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM2, value);
144 value = (panel_info.vl_col - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
145 value |= panel_info.vl_row - 1;
146 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDFRMCFG, value);
148 /* FIFO Threshold: Use formula from data sheet */
149 value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
150 lcdc_writel(panel_info.mmio, ATMEL_LCDC_FIFO, value);
152 /* Toggle LCD_MODE every frame */
153 lcdc_writel(panel_info.mmio, ATMEL_LCDC_MVAL, 0);
155 /* Disable all interrupts */
156 lcdc_writel(panel_info.mmio, ATMEL_LCDC_IDR, ~0UL);
159 value = ATMEL_LCDC_PS_DIV8 |
160 ATMEL_LCDC_ENA_PWMENABLE;
161 if (!panel_info.vl_cont_pol_low)
162 value |= ATMEL_LCDC_POL_POSITIVE;
163 lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value);
164 lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
166 /* Set framebuffer DMA base address and pixel offset */
167 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMABADDR1, (u_long)lcdbase);
169 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
170 lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
171 (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
174 ulong calc_fbsize(void)
176 return ((panel_info.vl_col * panel_info.vl_row *
177 NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;