5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
7 * Copyright (C) 2008-2009 MontaVista Software Inc.
8 * Copyright (C) 2008-2009 Texas Instruments Inc
10 * Based on the LCD driver for TI Avalanche processors written by
11 * Ajay Singh and Shalom Hai.
13 * SPDX-License-Identifier: GPL-2.0+
19 #include <linux/list.h>
22 #include <asm/errno.h>
24 #include <asm/arch/hardware.h>
26 #include "videomodes.h"
27 #include <asm/arch/da8xx-fb.h>
29 #define DRIVER_NAME "da8xx_lcdc"
31 /* LCD Status Register */
32 #define LCD_END_OF_FRAME1 (1 << 9)
33 #define LCD_END_OF_FRAME0 (1 << 8)
34 #define LCD_PL_LOAD_DONE (1 << 6)
35 #define LCD_FIFO_UNDERFLOW (1 << 5)
36 #define LCD_SYNC_LOST (1 << 2)
38 /* LCD DMA Control Register */
39 #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
40 #define LCD_DMA_BURST_1 0x0
41 #define LCD_DMA_BURST_2 0x1
42 #define LCD_DMA_BURST_4 0x2
43 #define LCD_DMA_BURST_8 0x3
44 #define LCD_DMA_BURST_16 0x4
45 #define LCD_END_OF_FRAME_INT_ENA (1 << 2)
46 #define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0)
48 /* LCD Control Register */
49 #define LCD_CLK_DIVISOR(x) ((x) << 8)
50 #define LCD_RASTER_MODE 0x01
52 /* LCD Raster Control Register */
53 #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
54 #define PALETTE_AND_DATA 0x00
55 #define PALETTE_ONLY 0x01
56 #define DATA_ONLY 0x02
58 #define LCD_MONO_8BIT_MODE (1 << 9)
59 #define LCD_RASTER_ORDER (1 << 8)
60 #define LCD_TFT_MODE (1 << 7)
61 #define LCD_UNDERFLOW_INT_ENA (1 << 6)
62 #define LCD_PL_ENABLE (1 << 4)
63 #define LCD_MONOCHROME_MODE (1 << 1)
64 #define LCD_RASTER_ENABLE (1 << 0)
65 #define LCD_TFT_ALT_ENABLE (1 << 23)
66 #define LCD_STN_565_ENABLE (1 << 24)
68 /* LCD Raster Timing 2 Register */
69 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
70 #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
71 #define LCD_SYNC_CTRL (1 << 25)
72 #define LCD_SYNC_EDGE (1 << 24)
73 #define LCD_INVERT_PIXEL_CLOCK (1 << 22)
74 #define LCD_INVERT_LINE_CLOCK (1 << 21)
75 #define LCD_INVERT_FRAME_CLOCK (1 << 20)
78 struct da8xx_lcd_regs {
96 u32 dma_frm_buf_base_addr_0;
97 u32 dma_frm_buf_ceiling_addr_0;
98 u32 dma_frm_buf_base_addr_1;
99 u32 dma_frm_buf_ceiling_addr_1;
102 #define LCD_NUM_BUFFERS 1
104 #define WSI_TIMEOUT 50
105 #define PALETTE_SIZE 256
106 #define LEFT_MARGIN 64
107 #define RIGHT_MARGIN 64
108 #define UPPER_MARGIN 32
109 #define LOWER_MARGIN 32
111 #define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
113 static struct da8xx_lcd_regs *da8xx_fb_reg_base;
115 DECLARE_GLOBAL_DATA_PTR;
118 static GraphicDevice gpanel;
119 static const struct da8xx_panel *lcd_panel;
120 static struct fb_info *da8xx_fb_info;
121 static int bits_x_pixel;
123 static inline unsigned int lcdc_read(u32 *addr)
125 return (unsigned int)readl(addr);
128 static inline void lcdc_write(unsigned int val, u32 *addr)
133 struct da8xx_fb_par {
135 unsigned char *v_palette_base;
136 dma_addr_t vram_phys;
137 unsigned long vram_size;
139 unsigned int dma_start;
140 unsigned int dma_end;
141 struct clk *lcdc_clk;
143 unsigned short pseudo_palette[16];
144 unsigned int palette_sz;
145 unsigned int pxl_clk;
152 /* Variable Screen Information */
153 static struct fb_var_screeninfo da8xx_fb_var = {
161 .pixclock = 46666, /* 46us - AUO display */
163 .left_margin = LEFT_MARGIN,
164 .right_margin = RIGHT_MARGIN,
165 .upper_margin = UPPER_MARGIN,
166 .lower_margin = LOWER_MARGIN,
168 .vmode = FB_VMODE_NONINTERLACED
171 static struct fb_fix_screeninfo da8xx_fb_fix = {
172 .id = "DA8xx FB Drv",
173 .type = FB_TYPE_PACKED_PIXELS,
175 .visual = FB_VISUAL_PSEUDOCOLOR,
179 .accel = FB_ACCEL_NONE
182 static const struct display_panel disp_panel = {
189 static const struct lcd_ctrl_config lcd_cfg = {
199 .invert_line_clock = 1,
200 .invert_frm_clock = 1,
206 /* Enable the Raster Engine of the LCD Controller */
207 static inline void lcd_enable_raster(void)
211 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
212 if (!(reg & LCD_RASTER_ENABLE))
213 lcdc_write(reg | LCD_RASTER_ENABLE,
214 &da8xx_fb_reg_base->raster_ctrl);
217 /* Disable the Raster Engine of the LCD Controller */
218 static inline void lcd_disable_raster(void)
222 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
223 if (reg & LCD_RASTER_ENABLE)
224 lcdc_write(reg & ~LCD_RASTER_ENABLE,
225 &da8xx_fb_reg_base->raster_ctrl);
228 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
235 /* init reg to clear PLM (loading mode) fields */
236 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
237 reg_ras &= ~(3 << 20);
239 reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
241 if (load_mode == LOAD_DATA) {
242 start = par->dma_start;
245 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
246 reg_dma |= LCD_END_OF_FRAME_INT_ENA;
248 #if (LCD_NUM_BUFFERS == 2)
249 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
250 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
251 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
252 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
253 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
255 reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE;
256 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
257 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
258 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
259 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
262 } else if (load_mode == LOAD_PALETTE) {
263 start = par->p_palette_base;
264 end = start + par->palette_sz - 1;
266 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
267 reg_ras |= LCD_PL_ENABLE;
269 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
270 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
273 lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);
274 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
277 * The Raster enable bit must be set after all other control fields are
283 /* Configure the Burst Size of DMA */
284 static int lcd_cfg_dma(int burst_size)
288 reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001;
289 switch (burst_size) {
291 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
294 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
297 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
300 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
303 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
308 lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);
313 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
317 /* Set the AC Bias Period and Number of Transisitons per Interrupt */
318 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
319 reg |= LCD_AC_BIAS_FREQUENCY(period) |
320 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
321 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
324 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
329 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf;
330 reg |= ((back_porch & 0xff) << 24)
331 | ((front_porch & 0xff) << 16)
332 | ((pulse_width & 0x3f) << 10);
333 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
336 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
341 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff;
342 reg |= ((back_porch & 0xff) << 24)
343 | ((front_porch & 0xff) << 16)
344 | ((pulse_width & 0x3f) << 10);
345 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
348 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
352 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
354 LCD_MONOCHROME_MODE);
356 switch (cfg->p_disp_panel->panel_shade) {
358 reg |= LCD_MONOCHROME_MODE;
359 if (cfg->mono_8bit_mode)
360 reg |= LCD_MONO_8BIT_MODE;
364 if (cfg->tft_alt_mode)
365 reg |= LCD_TFT_ALT_ENABLE;
369 if (cfg->stn_565_mode)
370 reg |= LCD_STN_565_ENABLE;
377 /* enable additional interrupts here */
378 reg |= LCD_UNDERFLOW_INT_ENA;
380 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
382 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
385 reg |= LCD_SYNC_CTRL;
387 reg &= ~LCD_SYNC_CTRL;
390 reg |= LCD_SYNC_EDGE;
392 reg &= ~LCD_SYNC_EDGE;
394 if (cfg->invert_line_clock)
395 reg |= LCD_INVERT_LINE_CLOCK;
397 reg &= ~LCD_INVERT_LINE_CLOCK;
399 if (cfg->invert_frm_clock)
400 reg |= LCD_INVERT_FRAME_CLOCK;
402 reg &= ~LCD_INVERT_FRAME_CLOCK;
404 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
409 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
410 u32 bpp, u32 raster_order)
414 /* Set the Panel Width */
415 /* Pixels per line = (PPL + 1)*16 */
416 /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
418 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
420 reg |= ((width >> 4) - 1) << 4;
421 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
423 /* Set the Panel Height */
424 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
425 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
426 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
428 /* Set the Raster Order of the Frame Buffer */
429 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
431 reg |= LCD_RASTER_ORDER;
432 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
439 par->palette_sz = 16 * 2;
443 par->palette_sz = 256 * 2;
453 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
454 unsigned blue, unsigned transp,
455 struct fb_info *info)
457 struct da8xx_fb_par *par = info->par;
458 unsigned short *palette = (unsigned short *) par->v_palette_base;
465 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
468 if (info->var.bits_per_pixel == 8) {
473 pal = (red & 0x0f00);
474 pal |= (green & 0x00f0);
475 pal |= (blue & 0x000f);
477 if (palette[regno] != pal) {
479 palette[regno] = pal;
481 } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
482 red >>= (16 - info->var.red.length);
483 red <<= info->var.red.offset;
485 green >>= (16 - info->var.green.length);
486 green <<= info->var.green.offset;
488 blue >>= (16 - info->var.blue.length);
489 blue <<= info->var.blue.offset;
491 par->pseudo_palette[regno] = red | green | blue;
493 if (palette[0] != 0x4000) {
499 /* Update the palette in the h/w as needed. */
501 lcd_blit(LOAD_PALETTE, par);
506 static void lcd_reset(struct da8xx_fb_par *par)
508 /* Disable the Raster if previously Enabled */
509 lcd_disable_raster();
511 /* DMA has to be disabled */
512 lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
513 lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
516 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
518 unsigned int lcd_clk, div;
520 /* Get clock from sysclk2 */
521 lcd_clk = clk_get(2);
523 div = lcd_clk / par->pxl_clk;
524 debug("LCD Clock: 0x%x Divider: 0x%x PixClk: 0x%x\n",
525 lcd_clk, div, par->pxl_clk);
527 /* Configure the LCD clock divisor. */
528 lcdc_write(LCD_CLK_DIVISOR(div) |
529 (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
532 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
533 const struct da8xx_panel *panel)
540 /* Calculate the divider */
541 lcd_calc_clk_divider(par);
543 if (panel->invert_pxl_clk)
544 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |
545 LCD_INVERT_PIXEL_CLOCK),
546 &da8xx_fb_reg_base->raster_timing_2);
548 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &
549 ~LCD_INVERT_PIXEL_CLOCK),
550 &da8xx_fb_reg_base->raster_timing_2);
552 /* Configure the DMA burst size. */
553 ret = lcd_cfg_dma(cfg->dma_burst_sz);
557 /* Configure the AC bias properties. */
558 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
560 /* Configure the vertical and horizontal sync properties. */
561 lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
562 lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
564 /* Configure for disply */
565 ret = lcd_cfg_display(cfg);
569 if (QVGA != cfg->p_disp_panel->panel_type)
572 if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
573 cfg->bpp >= cfg->p_disp_panel->min_bpp)
576 bpp = cfg->p_disp_panel->max_bpp;
579 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
580 (unsigned int)panel->height, bpp,
586 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |
587 (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl);
592 static void lcdc_dma_start(void)
594 struct da8xx_fb_par *par = da8xx_fb_info->par;
595 lcdc_write(par->dma_start,
596 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
597 lcdc_write(par->dma_end,
598 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
600 &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
602 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
605 static u32 lcdc_irq_handler(void)
607 struct da8xx_fb_par *par = da8xx_fb_info->par;
608 u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
611 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
612 debug("LCD_SYNC_LOST\n");
613 lcd_disable_raster();
614 lcdc_write(stat, &da8xx_fb_reg_base->stat);
616 return LCD_SYNC_LOST;
617 } else if (stat & LCD_PL_LOAD_DONE) {
618 debug("LCD_PL_LOAD_DONE\n");
620 * Must disable raster before changing state of any control bit.
621 * And also must be disabled before clearing the PL loading
622 * interrupt via the following write to the status register. If
623 * this is done after then one gets multiple PL done interrupts.
625 lcd_disable_raster();
627 lcdc_write(stat, &da8xx_fb_reg_base->stat);
629 /* Disable PL completion inerrupt */
630 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
631 reg_ras &= ~LCD_PL_ENABLE;
632 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
634 /* Setup and start data loading mode */
635 lcd_blit(LOAD_DATA, par);
636 return LCD_PL_LOAD_DONE;
638 lcdc_write(stat, &da8xx_fb_reg_base->stat);
640 if (stat & LCD_END_OF_FRAME0)
641 debug("LCD_END_OF_FRAME0\n");
643 lcdc_write(par->dma_start,
644 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
645 lcdc_write(par->dma_end,
646 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
648 return LCD_END_OF_FRAME0;
653 static u32 wait_for_event(u32 event)
659 ret = lcdc_irq_handler();
661 } while (!(ret & event));
664 printf("%s: event %d not hit\n", __func__, event);
672 void *video_hw_init(void)
674 struct da8xx_fb_par *par;
679 printf("Display not initialized\n");
682 gpanel.winSizeX = lcd_panel->width;
683 gpanel.winSizeY = lcd_panel->height;
684 gpanel.plnSizeX = lcd_panel->width;
685 gpanel.plnSizeY = lcd_panel->height;
687 switch (bits_x_pixel) {
689 gpanel.gdfBytesPP = 4;
690 gpanel.gdfIndex = GDF_32BIT_X888RGB;
693 gpanel.gdfBytesPP = 2;
694 gpanel.gdfIndex = GDF_16BIT_565RGB;
697 gpanel.gdfBytesPP = 1;
698 gpanel.gdfIndex = GDF__8BIT_INDEX;
702 da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DAVINCI_LCD_CNTL_BASE;
704 debug("Resolution: %dx%d %x\n",
709 size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
710 da8xx_fb_info = malloc(size);
711 debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
713 if (!da8xx_fb_info) {
714 printf("Memory allocation failed for fb_info\n");
717 memset(da8xx_fb_info, 0, size);
718 p = (char *)da8xx_fb_info;
719 da8xx_fb_info->par = p + sizeof(struct fb_info);
720 debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par);
722 par = da8xx_fb_info->par;
723 par->pxl_clk = lcd_panel->pxl_clk;
725 if (lcd_init(par, &lcd_cfg, lcd_panel) < 0) {
726 printf("lcd_init failed\n");
730 /* allocate frame buffer */
731 par->vram_size = lcd_panel->width * lcd_panel->height * lcd_cfg.bpp;
732 par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
734 par->vram_virt = malloc(par->vram_size);
736 par->vram_phys = (dma_addr_t) par->vram_virt;
737 debug("Requesting 0x%x bytes for framebuffer at 0x%x\n",
738 (unsigned int)par->vram_size,
739 (unsigned int)par->vram_virt);
740 if (!par->vram_virt) {
741 printf("GLCD: malloc for frame buffer failed\n");
745 gpanel.frameAdrs = (unsigned int)par->vram_virt;
746 da8xx_fb_info->screen_base = (char *) par->vram_virt;
747 da8xx_fb_fix.smem_start = gpanel.frameAdrs;
748 da8xx_fb_fix.smem_len = par->vram_size;
749 da8xx_fb_fix.line_length = (lcd_panel->width * lcd_cfg.bpp) / 8;
751 par->dma_start = par->vram_phys;
752 par->dma_end = par->dma_start + lcd_panel->height *
753 da8xx_fb_fix.line_length - 1;
755 /* allocate palette buffer */
756 par->v_palette_base = malloc(PALETTE_SIZE);
757 if (!par->v_palette_base) {
758 printf("GLCD: malloc for palette buffer failed\n");
759 goto err_release_fb_mem;
761 memset(par->v_palette_base, 0, PALETTE_SIZE);
762 par->p_palette_base = (unsigned int)par->v_palette_base;
765 da8xx_fb_info->var.bits_per_pixel = lcd_cfg.bpp;
767 da8xx_fb_var.xres = lcd_panel->width;
768 da8xx_fb_var.xres_virtual = lcd_panel->width;
770 da8xx_fb_var.yres = lcd_panel->height;
771 da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
773 da8xx_fb_var.grayscale =
774 lcd_cfg.p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
775 da8xx_fb_var.bits_per_pixel = lcd_cfg.bpp;
777 da8xx_fb_var.hsync_len = lcd_panel->hsw;
778 da8xx_fb_var.vsync_len = lcd_panel->vsw;
780 /* Initialize fbinfo */
781 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
782 da8xx_fb_info->fix = da8xx_fb_fix;
783 da8xx_fb_info->var = da8xx_fb_var;
784 da8xx_fb_info->pseudo_palette = par->pseudo_palette;
785 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
786 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
788 /* Clear interrupt */
789 memset((void *)par->vram_virt, 0, par->vram_size);
790 lcd_disable_raster();
791 lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
792 debug("Palette at 0x%x size %d\n", par->p_palette_base,
796 /* Load a default palette */
797 fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info);
799 /* Check that the palette is loaded */
800 wait_for_event(LCD_PL_LOAD_DONE);
802 /* Wait until DMA is working */
803 wait_for_event(LCD_END_OF_FRAME0);
805 return (void *)&gpanel;
808 free(par->vram_virt);
816 void video_set_lut(unsigned int index, /* color number */
817 unsigned char r, /* red */
818 unsigned char g, /* green */
819 unsigned char b /* blue */
826 void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel)
829 bits_x_pixel = bits_pixel;