2 * Copyright (C) 2012 Samsung Electronics
4 * Author: Donghwa Lee <dh09.lee@samsung.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <linux/err.h>
25 #include <asm/arch/cpu.h>
26 #include <asm/arch/dp_info.h>
27 #include <asm/arch/dp.h>
29 struct exynos_dp *dp_regs;
31 void exynos_dp_set_base_addr(void)
33 dp_regs = (struct exynos_dp *)samsung_get_base_dp();
36 static void exynos_dp_enable_video_input(unsigned int enable)
40 reg = readl(&dp_regs->video_ctl1);
41 reg &= ~VIDEO_EN_MASK;
43 /* enable video input*/
47 writel(reg, &dp_regs->video_ctl1);
52 void exynos_dp_enable_video_bist(unsigned int enable)
57 reg = readl(&dp_regs->video_ctl4);
58 reg &= ~VIDEO_BIST_MASK;
62 reg |= VIDEO_BIST_MASK;
64 writel(reg, &dp_regs->video_ctl4);
69 void exynos_dp_enable_video_mute(unsigned int enable)
73 reg = readl(&dp_regs->video_ctl1);
74 reg &= ~(VIDEO_MUTE_MASK);
76 reg |= VIDEO_MUTE_MASK;
78 writel(reg, &dp_regs->video_ctl1);
84 static void exynos_dp_init_analog_param(void)
90 * Normal bandgap, Normal swing, Tx terminal registor 61 ohm
91 * 24M Phy clock, TX digital logic power is 100:1.0625V
93 reg = SEL_BG_NEW_BANDGAP | TX_TERMINAL_CTRL_61_OHM |
94 SWING_A_30PER_G_NORMAL;
95 writel(reg, &dp_regs->analog_ctl1);
97 reg = SEL_24M | TX_DVDD_BIT_1_0625V;
98 writel(reg, &dp_regs->analog_ctl2);
101 * Set power source for internal clk driver to 1.0625v.
102 * Select current reference of TX driver current to 00:Ipp/2+Ic/2.
103 * Set VCO range of PLL +- 0uA
105 reg = DRIVE_DVDD_BIT_1_0625V | SEL_CURRENT_DEFAULT | VCO_BIT_000_MICRO;
106 writel(reg, &dp_regs->analog_ctl3);
109 * Set AUX TX terminal resistor to 102 ohm
110 * Set AUX channel amplitude control
112 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA;
113 writel(reg, &dp_regs->pll_filter_ctl1);
116 * PLL loop filter bandwidth
117 * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
118 * PLL digital power select: 1.2500V
120 reg = CH3_AMP_0_MV | CH2_AMP_0_MV | CH1_AMP_0_MV | CH0_AMP_0_MV;
122 writel(reg, &dp_regs->amp_tuning_ctl);
125 * PLL loop filter bandwidth
126 * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
127 * PLL digital power select: 1.1250V
129 reg = DP_PLL_LOOP_BIT_DEFAULT | DP_PLL_REF_BIT_1_1250V;
130 writel(reg, &dp_regs->pll_ctl);
133 static void exynos_dp_init_interrupt(void)
135 /* Set interrupt registers to initial states */
139 * INT pin assertion polarity. It must be configured
140 * correctly according to ICU setting.
141 * 1 = assert high, 0 = assert low
143 writel(INT_POL, &dp_regs->int_ctl);
145 /* Clear pending regisers */
146 writel(0xff, &dp_regs->common_int_sta1);
147 writel(0xff, &dp_regs->common_int_sta2);
148 writel(0xff, &dp_regs->common_int_sta3);
149 writel(0xff, &dp_regs->common_int_sta4);
150 writel(0xff, &dp_regs->int_sta);
152 /* 0:mask,1: unmask */
153 writel(0x00, &dp_regs->int_sta_mask1);
154 writel(0x00, &dp_regs->int_sta_mask2);
155 writel(0x00, &dp_regs->int_sta_mask3);
156 writel(0x00, &dp_regs->int_sta_mask4);
157 writel(0x00, &dp_regs->int_sta_mask);
160 void exynos_dp_reset(void)
162 unsigned int reg_func_1;
165 writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
167 exynos_dp_enable_video_input(DP_DISABLE);
168 exynos_dp_enable_video_bist(DP_DISABLE);
169 exynos_dp_enable_video_mute(DP_DISABLE);
172 reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
173 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
174 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
176 writel(reg_func_1, &dp_regs->func_en1);
177 writel(reg_func_1, &dp_regs->func_en2);
181 exynos_dp_init_analog_param();
182 exynos_dp_init_interrupt();
187 void exynos_dp_enable_sw_func(unsigned int enable)
191 reg = readl(&dp_regs->func_en1);
192 reg &= ~(SW_FUNC_EN_N);
197 writel(reg, &dp_regs->func_en1);
202 unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable)
206 reg = readl(&dp_regs->phy_pd);
239 reg &= ~(PHY_PD | AUX_PD | CH0_PD | CH1_PD | CH2_PD |
242 reg |= (PHY_PD | AUX_PD | CH0_PD | CH1_PD |
246 printf("DP undefined block number : %d\n", block);
250 writel(reg, &dp_regs->phy_pd);
255 unsigned int exynos_dp_get_pll_lock_status(void)
259 reg = readl(&dp_regs->debug_ctl);
267 static void exynos_dp_set_pll_power(unsigned int enable)
271 reg = readl(&dp_regs->pll_ctl);
277 writel(reg, &dp_regs->pll_ctl);
280 int exynos_dp_init_analog_func(void)
282 int ret = EXYNOS_DP_SUCCESS;
283 unsigned int retry_cnt = 10;
286 /*Power On All Analog block */
287 exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE);
290 writel(reg, &dp_regs->common_int_sta1);
292 reg = readl(&dp_regs->debug_ctl);
293 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
294 writel(reg, &dp_regs->debug_ctl);
296 /*Assert DP PLL Reset*/
297 reg = readl(&dp_regs->pll_ctl);
299 writel(reg, &dp_regs->pll_ctl);
303 /*Deassert DP PLL Reset*/
304 reg = readl(&dp_regs->pll_ctl);
305 reg &= ~(DP_PLL_RESET);
306 writel(reg, &dp_regs->pll_ctl);
308 exynos_dp_set_pll_power(DP_ENABLE);
310 while (exynos_dp_get_pll_lock_status() == PLL_UNLOCKED) {
313 if (retry_cnt == 0) {
314 printf("DP dp's pll lock failed : retry : %d\n",
320 debug("dp's pll lock success(%d)\n", retry_cnt);
322 /* Enable Serdes FIFO function and Link symbol clock domain module */
323 reg = readl(&dp_regs->func_en2);
324 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
326 writel(reg, &dp_regs->func_en2);
331 void exynos_dp_init_hpd(void)
335 /* Clear interrupts releated to Hot Plug Dectect */
336 reg = HOTPLUG_CHG | HPD_LOST | PLUG;
337 writel(reg, &dp_regs->common_int_sta4);
340 writel(reg, &dp_regs->int_sta);
342 reg = readl(&dp_regs->sys_ctl3);
343 reg &= ~(F_HPD | HPD_CTRL);
344 writel(reg, &dp_regs->sys_ctl3);
349 static inline void exynos_dp_reset_aux(void)
353 /* Disable AUX channel module */
354 reg = readl(&dp_regs->func_en2);
355 reg |= AUX_FUNC_EN_N;
356 writel(reg, &dp_regs->func_en2);
361 void exynos_dp_init_aux(void)
365 /* Clear inerrupts related to AUX channel */
366 reg = RPLY_RECEIV | AUX_ERR;
367 writel(reg, &dp_regs->int_sta);
369 exynos_dp_reset_aux();
371 /* Disable AUX transaction H/W retry */
372 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)|
373 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
374 writel(reg, &dp_regs->aux_hw_retry_ctl);
376 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
377 reg = DEFER_CTRL_EN | DEFER_COUNT(1);
378 writel(reg, &dp_regs->aux_ch_defer_ctl);
380 /* Enable AUX channel module */
381 reg = readl(&dp_regs->func_en2);
382 reg &= ~AUX_FUNC_EN_N;
383 writel(reg, &dp_regs->func_en2);
388 void exynos_dp_config_interrupt(void)
392 /* 0: mask, 1: unmask */
393 reg = COMMON_INT_MASK_1;
394 writel(reg, &dp_regs->common_int_mask1);
396 reg = COMMON_INT_MASK_2;
397 writel(reg, &dp_regs->common_int_mask2);
399 reg = COMMON_INT_MASK_3;
400 writel(reg, &dp_regs->common_int_mask3);
402 reg = COMMON_INT_MASK_4;
403 writel(reg, &dp_regs->common_int_mask4);
406 writel(reg, &dp_regs->int_sta_mask);
411 unsigned int exynos_dp_get_plug_in_status(void)
415 reg = readl(&dp_regs->sys_ctl3);
416 if (reg & HPD_STATUS)
422 unsigned int exynos_dp_detect_hpd(void)
424 int timeout_loop = DP_TIMEOUT_LOOP_COUNT;
428 while (exynos_dp_get_plug_in_status() != 0) {
429 if (timeout_loop == 0)
435 return EXYNOS_DP_SUCCESS;
438 unsigned int exynos_dp_start_aux_transaction(void)
441 unsigned int ret = 0;
442 unsigned int retry_cnt;
444 /* Enable AUX CH operation */
445 reg = readl(&dp_regs->aux_ch_ctl2);
447 writel(reg, &dp_regs->aux_ch_ctl2);
451 reg = readl(&dp_regs->int_sta);
452 if (!(reg & RPLY_RECEIV)) {
453 if (retry_cnt == 0) {
454 printf("DP Reply Timeout!!\n");
464 /* Clear interrupt source for AUX CH command reply */
465 writel(reg, &dp_regs->int_sta);
467 /* Clear interrupt source for AUX CH access error */
468 reg = readl(&dp_regs->int_sta);
470 printf("DP Aux Access Error\n");
471 writel(AUX_ERR, &dp_regs->int_sta);
476 /* Check AUX CH error access status */
477 reg = readl(&dp_regs->aux_ch_sta);
478 if ((reg & AUX_STATUS_MASK) != 0) {
479 debug("DP AUX CH error happens: %x\n", reg & AUX_STATUS_MASK);
484 return EXYNOS_DP_SUCCESS;
487 unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
490 unsigned int reg, ret;
492 /* Clear AUX CH data buffer */
494 writel(reg, &dp_regs->buffer_data_ctl);
496 /* Select DPCD device address */
497 reg = AUX_ADDR_7_0(reg_addr);
498 writel(reg, &dp_regs->aux_addr_7_0);
499 reg = AUX_ADDR_15_8(reg_addr);
500 writel(reg, &dp_regs->aux_addr_15_8);
501 reg = AUX_ADDR_19_16(reg_addr);
502 writel(reg, &dp_regs->aux_addr_19_16);
504 /* Write data buffer */
505 reg = (unsigned int)data;
506 writel(reg, &dp_regs->buf_data0);
509 * Set DisplayPort transaction and write 1 byte
510 * If bit 3 is 1, DisplayPort transaction.
511 * If Bit 3 is 0, I2C transaction.
513 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
514 writel(reg, &dp_regs->aux_ch_ctl1);
516 /* Start AUX transaction */
517 ret = exynos_dp_start_aux_transaction();
518 if (ret != EXYNOS_DP_SUCCESS) {
519 printf("DP Aux transaction failed\n");
526 unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
532 /* Clear AUX CH data buffer */
534 writel(reg, &dp_regs->buffer_data_ctl);
536 /* Select DPCD device address */
537 reg = AUX_ADDR_7_0(reg_addr);
538 writel(reg, &dp_regs->aux_addr_7_0);
539 reg = AUX_ADDR_15_8(reg_addr);
540 writel(reg, &dp_regs->aux_addr_15_8);
541 reg = AUX_ADDR_19_16(reg_addr);
542 writel(reg, &dp_regs->aux_addr_19_16);
545 * Set DisplayPort transaction and read 1 byte
546 * If bit 3 is 1, DisplayPort transaction.
547 * If Bit 3 is 0, I2C transaction.
549 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
550 writel(reg, &dp_regs->aux_ch_ctl1);
552 /* Start AUX transaction */
553 retval = exynos_dp_start_aux_transaction();
555 debug("DP Aux Transaction fail!\n");
557 /* Read data buffer */
558 reg = readl(&dp_regs->buf_data0);
559 *data = (unsigned char)(reg & 0xff);
564 unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
566 unsigned char data[])
569 unsigned int start_offset;
570 unsigned int cur_data_count;
571 unsigned int cur_data_idx;
572 unsigned int retry_cnt;
573 unsigned int ret = 0;
575 /* Clear AUX CH data buffer */
577 writel(reg, &dp_regs->buffer_data_ctl);
580 while (start_offset < count) {
581 /* Buffer size of AUX CH is 16 * 4bytes */
582 if ((count - start_offset) > 16)
585 cur_data_count = count - start_offset;
589 /* Select DPCD device address */
590 reg = AUX_ADDR_7_0(reg_addr + start_offset);
591 writel(reg, &dp_regs->aux_addr_7_0);
592 reg = AUX_ADDR_15_8(reg_addr + start_offset);
593 writel(reg, &dp_regs->aux_addr_15_8);
594 reg = AUX_ADDR_19_16(reg_addr + start_offset);
595 writel(reg, &dp_regs->aux_addr_19_16);
597 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
599 reg = data[start_offset + cur_data_idx];
600 writel(reg, (unsigned int)&dp_regs->buf_data0 +
604 * Set DisplayPort transaction and write
605 * If bit 3 is 1, DisplayPort transaction.
606 * If Bit 3 is 0, I2C transaction.
608 reg = AUX_LENGTH(cur_data_count) |
609 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
610 writel(reg, &dp_regs->aux_ch_ctl1);
612 /* Start AUX transaction */
613 ret = exynos_dp_start_aux_transaction();
614 if (ret != EXYNOS_DP_SUCCESS) {
615 if (retry_cnt == 0) {
616 printf("DP Aux Transaction failed\n");
623 start_offset += cur_data_count;
629 unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr,
631 unsigned char data[])
634 unsigned int start_offset;
635 unsigned int cur_data_count;
636 unsigned int cur_data_idx;
637 unsigned int retry_cnt;
638 unsigned int ret = 0;
640 /* Clear AUX CH data buffer */
642 writel(reg, &dp_regs->buffer_data_ctl);
645 while (start_offset < count) {
646 /* Buffer size of AUX CH is 16 * 4bytes */
647 if ((count - start_offset) > 16)
650 cur_data_count = count - start_offset;
654 /* Select DPCD device address */
655 reg = AUX_ADDR_7_0(reg_addr + start_offset);
656 writel(reg, &dp_regs->aux_addr_7_0);
657 reg = AUX_ADDR_15_8(reg_addr + start_offset);
658 writel(reg, &dp_regs->aux_addr_15_8);
659 reg = AUX_ADDR_19_16(reg_addr + start_offset);
660 writel(reg, &dp_regs->aux_addr_19_16);
662 * Set DisplayPort transaction and read
663 * If bit 3 is 1, DisplayPort transaction.
664 * If Bit 3 is 0, I2C transaction.
666 reg = AUX_LENGTH(cur_data_count) |
667 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
668 writel(reg, &dp_regs->aux_ch_ctl1);
670 /* Start AUX transaction */
671 ret = exynos_dp_start_aux_transaction();
672 if (ret != EXYNOS_DP_SUCCESS) {
673 if (retry_cnt == 0) {
674 printf("DP Aux Transaction failed\n");
682 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
684 reg = readl((unsigned int)&dp_regs->buf_data0 +
686 data[start_offset + cur_data_idx] = (unsigned char)reg;
689 start_offset += cur_data_count;
695 int exynos_dp_select_i2c_device(unsigned int device_addr,
696 unsigned int reg_addr)
701 /* Set EDID device address */
703 writel(reg, &dp_regs->aux_addr_7_0);
704 writel(0x0, &dp_regs->aux_addr_15_8);
705 writel(0x0, &dp_regs->aux_addr_19_16);
707 /* Set offset from base address of EDID device */
708 writel(reg_addr, &dp_regs->buf_data0);
711 * Set I2C transaction and write address
712 * If bit 3 is 1, DisplayPort transaction.
713 * If Bit 3 is 0, I2C transaction.
715 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
717 writel(reg, &dp_regs->aux_ch_ctl1);
719 /* Start AUX transaction */
720 retval = exynos_dp_start_aux_transaction();
722 printf("%s: DP Aux Transaction fail!\n", __func__);
727 int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
728 unsigned int reg_addr,
735 for (i = 0; i < 10; i++) {
736 /* Clear AUX CH data buffer */
738 writel(reg, &dp_regs->buffer_data_ctl);
740 /* Select EDID device */
741 retval = exynos_dp_select_i2c_device(device_addr, reg_addr);
743 printf("DP Select EDID device fail. retry !\n");
748 * Set I2C transaction and read data
749 * If bit 3 is 1, DisplayPort transaction.
750 * If Bit 3 is 0, I2C transaction.
752 reg = AUX_TX_COMM_I2C_TRANSACTION |
754 writel(reg, &dp_regs->aux_ch_ctl1);
756 /* Start AUX transaction */
757 retval = exynos_dp_start_aux_transaction();
758 if (retval != EXYNOS_DP_SUCCESS)
759 printf("%s: DP Aux Transaction fail!\n", __func__);
764 *data = readl(&dp_regs->buf_data0);
769 int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
770 unsigned int reg_addr, unsigned int count, unsigned char edid[])
774 unsigned int cur_data_idx;
775 unsigned int defer = 0;
778 for (i = 0; i < count; i += 16) { /* use 16 burst */
779 for (j = 0; j < 100; j++) {
780 /* Clear AUX CH data buffer */
782 writel(reg, &dp_regs->buffer_data_ctl);
784 /* Set normal AUX CH command */
785 reg = readl(&dp_regs->aux_ch_ctl2);
787 writel(reg, &dp_regs->aux_ch_ctl2);
790 * If Rx sends defer, Tx sends only reads
791 * request without sending addres
795 exynos_dp_select_i2c_device(device_addr,
800 if (retval == EXYNOS_DP_SUCCESS) {
802 * Set I2C transaction and write data
803 * If bit 3 is 1, DisplayPort transaction.
804 * If Bit 3 is 0, I2C transaction.
806 reg = AUX_LENGTH(16) |
807 AUX_TX_COMM_I2C_TRANSACTION |
809 writel(reg, &dp_regs->aux_ch_ctl1);
811 /* Start AUX transaction */
812 retval = exynos_dp_start_aux_transaction();
816 printf("DP Aux Transaction fail!\n");
818 /* Check if Rx sends defer */
819 reg = readl(&dp_regs->aux_rx_comm);
820 if (reg == AUX_RX_COMM_AUX_DEFER ||
821 reg == AUX_RX_COMM_I2C_DEFER) {
822 printf("DP Defer: %d\n\n", reg);
827 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
828 reg = readl((unsigned int)&dp_regs->buf_data0
830 edid[i + cur_data_idx] = (unsigned char)reg;
837 void exynos_dp_reset_macro(void)
841 reg = readl(&dp_regs->phy_test);
843 writel(reg, &dp_regs->phy_test);
845 /* 10 us is the minimum Macro reset time. */
849 writel(reg, &dp_regs->phy_test);
852 void exynos_dp_set_link_bandwidth(unsigned char bwtype)
856 reg = (unsigned int)bwtype;
858 /* Set bandwidth to 2.7G or 1.62G */
859 if ((bwtype == DP_LANE_BW_1_62) || (bwtype == DP_LANE_BW_2_70))
860 writel(reg, &dp_regs->link_bw_set);
863 unsigned char exynos_dp_get_link_bandwidth(void)
868 reg = readl(&dp_regs->link_bw_set);
869 ret = (unsigned char)reg;
874 void exynos_dp_set_lane_count(unsigned char count)
878 reg = (unsigned int)count;
880 if ((count == DP_LANE_CNT_1) || (count == DP_LANE_CNT_2) ||
881 (count == DP_LANE_CNT_4))
882 writel(reg, &dp_regs->lane_count_set);
885 unsigned int exynos_dp_get_lane_count(void)
889 reg = readl(&dp_regs->lane_count_set);
894 unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt)
896 unsigned int reg_list[DP_LANE_CNT_4] = {
897 (unsigned int)&dp_regs->ln0_link_training_ctl,
898 (unsigned int)&dp_regs->ln1_link_training_ctl,
899 (unsigned int)&dp_regs->ln2_link_training_ctl,
900 (unsigned int)&dp_regs->ln3_link_training_ctl,
903 return readl(reg_list[lanecnt]);
906 void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
907 unsigned char lanecnt)
909 unsigned int reg_list[DP_LANE_CNT_4] = {
910 (unsigned int)&dp_regs->ln0_link_training_ctl,
911 (unsigned int)&dp_regs->ln1_link_training_ctl,
912 (unsigned int)&dp_regs->ln2_link_training_ctl,
913 (unsigned int)&dp_regs->ln3_link_training_ctl,
916 writel(request_val, reg_list[lanecnt]);
919 void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt)
923 unsigned int reg_list[DP_LANE_CNT_4] = {
924 (unsigned int)&dp_regs->ln0_link_training_ctl,
925 (unsigned int)&dp_regs->ln1_link_training_ctl,
926 (unsigned int)&dp_regs->ln2_link_training_ctl,
927 (unsigned int)&dp_regs->ln3_link_training_ctl,
929 unsigned int reg_shift[DP_LANE_CNT_4] = {
930 PRE_EMPHASIS_SET_0_SHIFT,
931 PRE_EMPHASIS_SET_1_SHIFT,
932 PRE_EMPHASIS_SET_2_SHIFT,
933 PRE_EMPHASIS_SET_3_SHIFT
936 for (i = 0; i < lanecnt; i++) {
937 reg = level << reg_shift[i];
938 writel(reg, reg_list[i]);
942 void exynos_dp_set_training_pattern(unsigned int pattern)
944 unsigned int reg = 0;
948 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
951 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
954 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
957 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
960 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_DISABLE |
961 SW_TRAINING_PATTERN_SET_NORMAL;
967 writel(reg, &dp_regs->training_ptn_set);
970 void exynos_dp_enable_enhanced_mode(unsigned char enable)
974 reg = readl(&dp_regs->sys_ctl4);
980 writel(reg, &dp_regs->sys_ctl4);
983 void exynos_dp_enable_scrambling(unsigned int enable)
987 reg = readl(&dp_regs->training_ptn_set);
988 reg &= ~(SCRAMBLING_DISABLE);
991 reg |= SCRAMBLING_DISABLE;
993 writel(reg, &dp_regs->training_ptn_set);
996 int exynos_dp_init_video(void)
1000 /* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */
1001 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1002 writel(reg, &dp_regs->common_int_sta1);
1004 /* I_STRM__CLK detect : DE_CTL : Auto detect */
1006 writel(reg, &dp_regs->sys_ctl1);
1011 void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
1015 /* Video Slave mode setting */
1016 reg = readl(&dp_regs->func_en1);
1017 reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1018 reg |= MASTER_VID_FUNC_EN_N;
1019 writel(reg, &dp_regs->func_en1);
1021 /* Configure Interlaced for slave mode video */
1022 reg = readl(&dp_regs->video_ctl10);
1023 reg &= ~INTERACE_SCAN_CFG;
1024 reg |= (video_info->interlaced << INTERACE_SCAN_CFG_SHIFT);
1025 writel(reg, &dp_regs->video_ctl10);
1027 /* Configure V sync polarity for slave mode video */
1028 reg = readl(&dp_regs->video_ctl10);
1029 reg &= ~VSYNC_POLARITY_CFG;
1030 reg |= (video_info->v_sync_polarity << V_S_POLARITY_CFG_SHIFT);
1031 writel(reg, &dp_regs->video_ctl10);
1033 /* Configure H sync polarity for slave mode video */
1034 reg = readl(&dp_regs->video_ctl10);
1035 reg &= ~HSYNC_POLARITY_CFG;
1036 reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
1037 writel(reg, &dp_regs->video_ctl10);
1039 /*Set video mode to slave mode */
1040 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1041 writel(reg, &dp_regs->soc_general_ctl);
1044 void exynos_dp_set_video_color_format(struct edp_video_info *video_info)
1048 /* Configure the input color depth, color space, dynamic range */
1049 reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) |
1050 (video_info->color_depth << IN_BPC_SHIFT) |
1051 (video_info->color_space << IN_COLOR_F_SHIFT);
1052 writel(reg, &dp_regs->video_ctl2);
1054 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1055 reg = readl(&dp_regs->video_ctl3);
1056 reg &= ~IN_YC_COEFFI_MASK;
1057 if (video_info->ycbcr_coeff)
1058 reg |= IN_YC_COEFFI_ITU709;
1060 reg |= IN_YC_COEFFI_ITU601;
1061 writel(reg, &dp_regs->video_ctl3);
1064 int exynos_dp_config_video_bist(struct edp_device_info *edp_info)
1067 unsigned int bist_type = 0;
1068 struct edp_video_info video_info = edp_info->video_info;
1070 /* For master mode, you don't need to set the video format */
1071 if (video_info.master_mode == 0) {
1072 writel(TOTAL_LINE_CFG_L(edp_info->disp_info.v_total),
1073 &dp_regs->total_ln_cfg_l);
1074 writel(TOTAL_LINE_CFG_H(edp_info->disp_info.v_total),
1075 &dp_regs->total_ln_cfg_h);
1076 writel(ACTIVE_LINE_CFG_L(edp_info->disp_info.v_res),
1077 &dp_regs->active_ln_cfg_l);
1078 writel(ACTIVE_LINE_CFG_H(edp_info->disp_info.v_res),
1079 &dp_regs->active_ln_cfg_h);
1080 writel(edp_info->disp_info.v_sync_width,
1082 writel(edp_info->disp_info.v_back_porch,
1084 writel(edp_info->disp_info.v_front_porch,
1087 writel(TOTAL_PIXEL_CFG_L(edp_info->disp_info.h_total),
1088 &dp_regs->total_pix_cfg_l);
1089 writel(TOTAL_PIXEL_CFG_H(edp_info->disp_info.h_total),
1090 &dp_regs->total_pix_cfg_h);
1091 writel(ACTIVE_PIXEL_CFG_L(edp_info->disp_info.h_res),
1092 &dp_regs->active_pix_cfg_l);
1093 writel(ACTIVE_PIXEL_CFG_H(edp_info->disp_info.h_res),
1094 &dp_regs->active_pix_cfg_h);
1095 writel(H_F_PORCH_CFG_L(edp_info->disp_info.h_front_porch),
1096 &dp_regs->hfp_cfg_l);
1097 writel(H_F_PORCH_CFG_H(edp_info->disp_info.h_front_porch),
1098 &dp_regs->hfp_cfg_h);
1099 writel(H_SYNC_PORCH_CFG_L(edp_info->disp_info.h_sync_width),
1100 &dp_regs->hsw_cfg_l);
1101 writel(H_SYNC_PORCH_CFG_H(edp_info->disp_info.h_sync_width),
1102 &dp_regs->hsw_cfg_h);
1103 writel(H_B_PORCH_CFG_L(edp_info->disp_info.h_back_porch),
1104 &dp_regs->hbp_cfg_l);
1105 writel(H_B_PORCH_CFG_H(edp_info->disp_info.h_back_porch),
1106 &dp_regs->hbp_cfg_h);
1109 * Set SLAVE_I_SCAN_CFG[2], VSYNC_P_CFG[1],
1110 * HSYNC_P_CFG[0] properly
1112 reg = (video_info.interlaced << INTERACE_SCAN_CFG_SHIFT |
1113 video_info.v_sync_polarity << V_S_POLARITY_CFG_SHIFT |
1114 video_info.h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
1115 writel(reg, &dp_regs->video_ctl10);
1118 /* BIST color bar width set--set to each bar is 32 pixel width */
1119 switch (video_info.bist_pattern) {
1121 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1122 BIST_TYPE_COLOR_BAR;
1125 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1126 BIST_TYPE_COLOR_BAR;
1128 case WHITE_GRAY_BALCKBAR_32:
1129 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1130 BIST_TYPE_WHITE_GRAY_BLACK_BAR;
1132 case WHITE_GRAY_BALCKBAR_64:
1133 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1134 BIST_TYPE_WHITE_GRAY_BLACK_BAR;
1136 case MOBILE_WHITEBAR_32:
1137 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1138 BIST_TYPE_MOBILE_WHITE_BAR;
1140 case MOBILE_WHITEBAR_64:
1141 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1142 BIST_TYPE_MOBILE_WHITE_BAR;
1149 writel(reg, &dp_regs->video_ctl4);
1154 unsigned int exynos_dp_is_slave_video_stream_clock_on(void)
1158 /* Update Video stream clk detect status */
1159 reg = readl(&dp_regs->sys_ctl1);
1160 writel(reg, &dp_regs->sys_ctl1);
1162 reg = readl(&dp_regs->sys_ctl1);
1164 if (!(reg & DET_STA)) {
1165 debug("DP Input stream clock not detected.\n");
1169 return EXYNOS_DP_SUCCESS;
1172 void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
1173 unsigned int n_value)
1177 if (type == REGISTER_M) {
1178 reg = readl(&dp_regs->sys_ctl4);
1180 writel(reg, &dp_regs->sys_ctl4);
1181 reg = M_VID0_CFG(m_value);
1182 writel(reg, &dp_regs->m_vid0);
1183 reg = M_VID1_CFG(m_value);
1184 writel(reg, &dp_regs->m_vid1);
1185 reg = M_VID2_CFG(m_value);
1186 writel(reg, &dp_regs->m_vid2);
1188 reg = N_VID0_CFG(n_value);
1189 writel(reg, &dp_regs->n_vid0);
1190 reg = N_VID1_CFG(n_value);
1191 writel(reg, &dp_regs->n_vid1);
1192 reg = N_VID2_CFG(n_value);
1193 writel(reg, &dp_regs->n_vid2);
1195 reg = readl(&dp_regs->sys_ctl4);
1197 writel(reg, &dp_regs->sys_ctl4);
1201 void exynos_dp_set_video_timing_mode(unsigned int type)
1205 reg = readl(&dp_regs->video_ctl10);
1208 if (type != VIDEO_TIMING_FROM_CAPTURE)
1211 writel(reg, &dp_regs->video_ctl10);
1214 void exynos_dp_enable_video_master(unsigned int enable)
1218 reg = readl(&dp_regs->soc_general_ctl);
1220 reg &= ~VIDEO_MODE_MASK;
1221 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1223 reg &= ~VIDEO_MODE_MASK;
1224 reg |= VIDEO_MODE_SLAVE_MODE;
1227 writel(reg, &dp_regs->soc_general_ctl);
1230 void exynos_dp_start_video(void)
1234 /* Enable Video input and disable Mute */
1235 reg = readl(&dp_regs->video_ctl1);
1237 writel(reg, &dp_regs->video_ctl1);
1240 unsigned int exynos_dp_is_video_stream_on(void)
1244 /* Update STRM_VALID */
1245 reg = readl(&dp_regs->sys_ctl3);
1246 writel(reg, &dp_regs->sys_ctl3);
1248 reg = readl(&dp_regs->sys_ctl3);
1249 if (!(reg & STRM_VALID))
1252 return EXYNOS_DP_SUCCESS;