2 * Copyright (C) 2012 Samsung Electronics
4 * Author: InKi Dae <inki.dae@samsung.com>
5 * Author: Donghwa Lee <dh09.lee@samsung.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/clk.h>
29 #include <asm/arch/clock.h>
30 #include <asm/arch/cpu.h>
31 #include "exynos_fb.h"
33 static unsigned long *lcd_base_addr;
34 static vidinfo_t *pvid;
36 void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,
39 lcd_base_addr = (unsigned long *)screen_base;
42 static void exynos_fimd_set_dualrgb(unsigned int enabled)
44 struct exynos_fb *fimd_ctrl =
45 (struct exynos_fb *)samsung_get_base_fimd();
49 cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
50 EXYNOS_DUALRGB_VDEN_EN_ENABLE;
52 /* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
53 cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col / 2) |
54 EXYNOS_DUALRGB_MAIN_CNT(0);
57 writel(cfg, &fimd_ctrl->dualrgb);
60 static void exynos_fimd_set_par(unsigned int win_id)
63 struct exynos_fb *fimd_ctrl =
64 (struct exynos_fb *)samsung_get_base_fimd();
66 /* set window control */
67 cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
68 EXYNOS_WINCON(win_id));
70 cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
71 EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
72 EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
73 EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
76 cfg |= EXYNOS_WINCON_DATAPATH_DMA;
79 cfg |= EXYNOS_WINCON_WSWP_ENABLE;
82 cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
84 /* pixel format is unpacked RGB888 */
85 cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
87 writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
88 EXYNOS_WINCON(win_id));
90 /* set window position to x=0, y=0*/
91 cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
92 writel(cfg, (unsigned int)&fimd_ctrl->vidosd0a +
93 EXYNOS_VIDOSD(win_id));
95 cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
96 EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1) |
97 EXYNOS_VIDOSD_RIGHT_X_E(1) |
98 EXYNOS_VIDOSD_BOTTOM_Y_E(0);
100 writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b +
101 EXYNOS_VIDOSD(win_id));
103 /* set window size for window0*/
104 cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
105 writel(cfg, (unsigned int)&fimd_ctrl->vidosd0c +
106 EXYNOS_VIDOSD(win_id));
109 static void exynos_fimd_set_buffer_address(unsigned int win_id)
111 unsigned long start_addr, end_addr;
112 struct exynos_fb *fimd_ctrl =
113 (struct exynos_fb *)samsung_get_base_fimd();
115 start_addr = (unsigned long)lcd_base_addr;
116 end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) *
119 writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 +
120 EXYNOS_BUFFER_OFFSET(win_id));
121 writel(end_addr, (unsigned int)&fimd_ctrl->vidw00add1b0 +
122 EXYNOS_BUFFER_OFFSET(win_id));
125 static void exynos_fimd_set_clock(vidinfo_t *pvid)
127 unsigned int cfg = 0, div = 0, remainder, remainder_div;
128 unsigned long pixel_clock;
129 unsigned long long src_clock;
130 struct exynos_fb *fimd_ctrl =
131 (struct exynos_fb *)samsung_get_base_fimd();
133 if (pvid->dual_lcd_enabled) {
134 pixel_clock = pvid->vl_freq *
135 (pvid->vl_hspw + pvid->vl_hfpd +
136 pvid->vl_hbpd + pvid->vl_col / 2) *
137 (pvid->vl_vspw + pvid->vl_vfpd +
138 pvid->vl_vbpd + pvid->vl_row);
139 } else if (pvid->interface_mode == FIMD_CPU_INTERFACE) {
140 pixel_clock = pvid->vl_freq *
141 pvid->vl_width * pvid->vl_height *
142 (pvid->cs_setup + pvid->wr_setup +
143 pvid->wr_act + pvid->wr_hold + 1);
145 pixel_clock = pvid->vl_freq *
146 (pvid->vl_hspw + pvid->vl_hfpd +
147 pvid->vl_hbpd + pvid->vl_col) *
148 (pvid->vl_vspw + pvid->vl_vfpd +
149 pvid->vl_vbpd + pvid->vl_row);
152 cfg = readl(&fimd_ctrl->vidcon0);
153 cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
154 EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
155 EXYNOS_VIDCON0_CLKDIR_MASK);
156 cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
157 EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
159 src_clock = (unsigned long long) get_lcd_clk();
161 /* get quotient and remainder. */
162 remainder = do_div(src_clock, pixel_clock);
166 remainder_div = remainder / pixel_clock;
168 /* round about one places of decimals. */
169 if (remainder_div >= 5)
172 /* in case of dual lcd mode. */
173 if (pvid->dual_lcd_enabled)
176 cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
177 writel(cfg, &fimd_ctrl->vidcon0);
180 void exynos_set_trigger(void)
182 unsigned int cfg = 0;
183 struct exynos_fb *fimd_ctrl =
184 (struct exynos_fb *)samsung_get_base_fimd();
186 cfg = readl(&fimd_ctrl->trigcon);
188 cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
190 writel(cfg, &fimd_ctrl->trigcon);
193 int exynos_is_i80_frame_done(void)
195 unsigned int cfg = 0;
197 struct exynos_fb *fimd_ctrl =
198 (struct exynos_fb *)samsung_get_base_fimd();
200 cfg = readl(&fimd_ctrl->trigcon);
202 /* frame done func is valid only when TRIMODE[0] is set to 1. */
203 status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
204 EXYNOS_I80STATUS_TRIG_DONE;
209 static void exynos_fimd_lcd_on(void)
211 unsigned int cfg = 0;
212 struct exynos_fb *fimd_ctrl =
213 (struct exynos_fb *)samsung_get_base_fimd();
216 cfg = readl(&fimd_ctrl->vidcon0);
217 cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
218 writel(cfg, &fimd_ctrl->vidcon0);
221 static void exynos_fimd_window_on(unsigned int win_id)
223 unsigned int cfg = 0;
224 struct exynos_fb *fimd_ctrl =
225 (struct exynos_fb *)samsung_get_base_fimd();
228 cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
229 EXYNOS_WINCON(win_id));
230 cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
231 writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
232 EXYNOS_WINCON(win_id));
234 cfg = readl(&fimd_ctrl->winshmap);
235 cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
236 writel(cfg, &fimd_ctrl->winshmap);
239 void exynos_fimd_lcd_off(void)
241 unsigned int cfg = 0;
242 struct exynos_fb *fimd_ctrl =
243 (struct exynos_fb *)samsung_get_base_fimd();
245 cfg = readl(&fimd_ctrl->vidcon0);
246 cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
247 writel(cfg, &fimd_ctrl->vidcon0);
250 void exynos_fimd_window_off(unsigned int win_id)
252 unsigned int cfg = 0;
253 struct exynos_fb *fimd_ctrl =
254 (struct exynos_fb *)samsung_get_base_fimd();
256 cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
257 EXYNOS_WINCON(win_id));
258 cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
259 writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
260 EXYNOS_WINCON(win_id));
262 cfg = readl(&fimd_ctrl->winshmap);
263 cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
264 writel(cfg, &fimd_ctrl->winshmap);
268 void exynos_fimd_lcd_init(vidinfo_t *vid)
270 unsigned int cfg = 0, rgb_mode;
272 struct exynos_fb *fimd_ctrl =
273 (struct exynos_fb *)samsung_get_base_fimd();
275 offset = exynos_fimd_get_base_offset();
277 /* store panel info to global variable */
280 rgb_mode = vid->rgb_mode;
282 if (vid->interface_mode == FIMD_RGB_INTERFACE) {
283 cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
284 writel(cfg, &fimd_ctrl->vidcon0);
286 cfg = readl(&fimd_ctrl->vidcon2);
287 cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
288 EXYNOS_VIDCON2_TVFORMATSEL_MASK |
289 EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
290 cfg |= EXYNOS_VIDCON2_WB_DISABLE;
291 writel(cfg, &fimd_ctrl->vidcon2);
296 cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
298 cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
300 cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
302 cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
304 writel(cfg, (unsigned int)&fimd_ctrl->vidcon1 + offset);
307 cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
308 cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
309 cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1);
310 writel(cfg, (unsigned int)&fimd_ctrl->vidtcon0 + offset);
312 cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
313 cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
314 cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1);
316 writel(cfg, (unsigned int)&fimd_ctrl->vidtcon1 + offset);
319 cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1) |
320 EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1) |
321 EXYNOS_VIDTCON2_HOZVAL_E(pvid->vl_col - 1) |
322 EXYNOS_VIDTCON2_LINEVAL_E(pvid->vl_row - 1);
324 writel(cfg, (unsigned int)&fimd_ctrl->vidtcon2 + offset);
327 /* set display mode */
328 cfg = readl(&fimd_ctrl->vidcon0);
329 cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
330 cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
331 writel(cfg, &fimd_ctrl->vidcon0);
334 exynos_fimd_set_par(pvid->win_id);
336 /* set memory address */
337 exynos_fimd_set_buffer_address(pvid->win_id);
339 /* set buffer size */
340 cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) |
341 EXYNOS_VIDADDR_PAGEWIDTH_E(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) |
342 EXYNOS_VIDADDR_OFFSIZE(0) |
343 EXYNOS_VIDADDR_OFFSIZE_E(0);
345 writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 +
346 EXYNOS_BUFFER_SIZE(pvid->win_id));
349 exynos_fimd_set_clock(pvid);
351 /* set rgb mode to dual lcd. */
352 exynos_fimd_set_dualrgb(pvid->dual_lcd_enabled);
355 exynos_fimd_lcd_on();
358 exynos_fimd_window_on(pvid->win_id);
361 unsigned long exynos_fimd_calc_fbsize(void)
363 return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8);