2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * FSL DCU Framebuffer driver
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <fdt_support.h>
12 #include <fsl_dcu_fb.h>
16 #include "videomodes.h"
18 /* Convert the X,Y resolution pair into a single number */
19 #define RESOLUTION(x, y) (((u32)(x) << 16) | (y))
21 #ifdef CONFIG_SYS_FSL_DCU_LE
22 #define dcu_read32 in_le32
23 #define dcu_write32 out_le32
24 #elif defined(CONFIG_SYS_FSL_DCU_BE)
25 #define dcu_read32 in_be32
26 #define dcu_write32 out_be32
29 #define DCU_MODE_BLEND_ITER(x) ((x) << 20)
30 #define DCU_MODE_RASTER_EN (1 << 14)
31 #define DCU_MODE_NORMAL 1
32 #define DCU_MODE_COLORBAR 3
33 #define DCU_BGND_R(x) ((x) << 16)
34 #define DCU_BGND_G(x) ((x) << 8)
35 #define DCU_BGND_B(x) (x)
36 #define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16)
37 #define DCU_DISP_SIZE_DELTA_X(x) (x)
38 #define DCU_HSYN_PARA_BP(x) ((x) << 22)
39 #define DCU_HSYN_PARA_PW(x) ((x) << 11)
40 #define DCU_HSYN_PARA_FP(x) (x)
41 #define DCU_VSYN_PARA_BP(x) ((x) << 22)
42 #define DCU_VSYN_PARA_PW(x) ((x) << 11)
43 #define DCU_VSYN_PARA_FP(x) (x)
44 #define DCU_SYN_POL_INV_PXCK_FALL (0 << 6)
45 #define DCU_SYN_POL_NEG_REMAIN (0 << 5)
46 #define DCU_SYN_POL_INV_VS_LOW (1 << 1)
47 #define DCU_SYN_POL_INV_HS_LOW (1)
48 #define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16)
49 #define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8)
50 #define DCU_THRESHOLD_OUT_BUF_LOW(x) (x)
51 #define DCU_UPDATE_MODE_MODE (1 << 31)
52 #define DCU_UPDATE_MODE_READREG (1 << 30)
54 #define DCU_CTRLDESCLN_1_HEIGHT(x) ((x) << 16)
55 #define DCU_CTRLDESCLN_1_WIDTH(x) (x)
56 #define DCU_CTRLDESCLN_2_POSY(x) ((x) << 16)
57 #define DCU_CTRLDESCLN_2_POSX(x) (x)
58 #define DCU_CTRLDESCLN_4_EN (1 << 31)
59 #define DCU_CTRLDESCLN_4_TILE_EN (1 << 30)
60 #define DCU_CTRLDESCLN_4_DATA_SEL_CLUT (1 << 29)
61 #define DCU_CTRLDESCLN_4_SAFETY_EN (1 << 28)
62 #define DCU_CTRLDESCLN_4_TRANS(x) ((x) << 20)
63 #define DCU_CTRLDESCLN_4_BPP(x) ((x) << 16)
64 #define DCU_CTRLDESCLN_4_RLE_EN (1 << 15)
65 #define DCU_CTRLDESCLN_4_LUOFFS(x) ((x) << 4)
66 #define DCU_CTRLDESCLN_4_BB_ON (1 << 2)
67 #define DCU_CTRLDESCLN_4_AB(x) (x)
68 #define DCU_CTRLDESCLN_5_CKMAX_R(x) ((x) << 16)
69 #define DCU_CTRLDESCLN_5_CKMAX_G(x) ((x) << 8)
70 #define DCU_CTRLDESCLN_5_CKMAX_B(x) (x)
71 #define DCU_CTRLDESCLN_6_CKMIN_R(x) ((x) << 16)
72 #define DCU_CTRLDESCLN_6_CKMIN_G(x) ((x) << 8)
73 #define DCU_CTRLDESCLN_6_CKMIN_B(x) (x)
74 #define DCU_CTRLDESCLN_7_TILE_VER(x) ((x) << 16)
75 #define DCU_CTRLDESCLN_7_TILE_HOR(x) (x)
76 #define DCU_CTRLDESCLN_8_FG_FCOLOR(x) (x)
77 #define DCU_CTRLDESCLN_9_BG_BCOLOR(x) (x)
79 #define BPP_16_RGB565 4
80 #define BPP_24_RGB888 5
81 #define BPP_32_ARGB8888 6
83 DECLARE_GLOBAL_DATA_PTR;
86 * This setting is used for the TWR_LCD_RGB card
88 static struct fb_videomode fsl_dcu_mode_480_272 = {
100 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
101 .vmode = FB_VMODE_NONINTERLACED
105 * This setting is used for Siliconimage SiI9022A HDMI
107 static struct fb_videomode fsl_dcu_mode_640_480 = {
108 .name = "640x480-60",
120 .vmode = FB_VMODE_NONINTERLACED,
141 u8 res_064[0x6c-0x64];
142 u32 parr_err_status1;
143 u8 res_070[0x7c-0x70];
144 u32 parr_err_status3;
145 u32 mparr_err_status1;
146 u8 res_084[0x90-0x84];
147 u32 mparr_err_status3;
148 u32 threshold_inp_buf[2];
149 u8 res_09c[0xa0-0x9c];
160 u8 res_0c4[0xcc-0xc8];
163 u8 res_0d4[0x100-0xd4];
170 u8 res_120[0x200-0x120];
171 u32 ctrldescl[DCU_LAYER_MAX_NUM][16];
174 static struct fb_info info;
176 static void reset_total_layers(void)
178 struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
181 for (i = 0; i < DCU_LAYER_MAX_NUM; i++) {
182 dcu_write32(®s->ctrldescl[i][0], 0);
183 dcu_write32(®s->ctrldescl[i][1], 0);
184 dcu_write32(®s->ctrldescl[i][2], 0);
185 dcu_write32(®s->ctrldescl[i][3], 0);
186 dcu_write32(®s->ctrldescl[i][4], 0);
187 dcu_write32(®s->ctrldescl[i][5], 0);
188 dcu_write32(®s->ctrldescl[i][6], 0);
189 dcu_write32(®s->ctrldescl[i][7], 0);
190 dcu_write32(®s->ctrldescl[i][8], 0);
191 dcu_write32(®s->ctrldescl[i][9], 0);
192 dcu_write32(®s->ctrldescl[i][10], 0);
195 dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG);
198 static int layer_ctrldesc_init(int index, u32 pixel_format)
200 struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
201 unsigned int bpp = BPP_24_RGB888;
203 dcu_write32(®s->ctrldescl[index][0],
204 DCU_CTRLDESCLN_1_HEIGHT(info.var.yres) |
205 DCU_CTRLDESCLN_1_WIDTH(info.var.xres));
207 dcu_write32(®s->ctrldescl[index][1],
208 DCU_CTRLDESCLN_2_POSY(0) |
209 DCU_CTRLDESCLN_2_POSX(0));
211 dcu_write32(®s->ctrldescl[index][2], (unsigned int)info.screen_base);
213 switch (pixel_format) {
221 bpp = BPP_32_ARGB8888;
224 printf("unsupported color depth: %u\n", pixel_format);
227 dcu_write32(®s->ctrldescl[index][3],
228 DCU_CTRLDESCLN_4_EN |
229 DCU_CTRLDESCLN_4_TRANS(0xff) |
230 DCU_CTRLDESCLN_4_BPP(bpp) |
231 DCU_CTRLDESCLN_4_AB(0));
233 dcu_write32(®s->ctrldescl[index][4],
234 DCU_CTRLDESCLN_5_CKMAX_R(0xff) |
235 DCU_CTRLDESCLN_5_CKMAX_G(0xff) |
236 DCU_CTRLDESCLN_5_CKMAX_B(0xff));
237 dcu_write32(®s->ctrldescl[index][5],
238 DCU_CTRLDESCLN_6_CKMIN_R(0) |
239 DCU_CTRLDESCLN_6_CKMIN_G(0) |
240 DCU_CTRLDESCLN_6_CKMIN_B(0));
242 dcu_write32(®s->ctrldescl[index][6],
243 DCU_CTRLDESCLN_7_TILE_VER(0) |
244 DCU_CTRLDESCLN_7_TILE_HOR(0));
246 dcu_write32(®s->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0));
247 dcu_write32(®s->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0));
249 dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG);
254 int fsl_dcu_init(unsigned int xres, unsigned int yres,
255 unsigned int pixel_format)
257 struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
258 unsigned int div, mode;
261 info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8);
263 if (info.screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) {
264 info.screen_size = 0;
268 /* Reserve framebuffer at the end of memory */
269 gd->fb_base = gd->bd->bi_dram[0].start +
270 gd->bd->bi_dram[0].size - info.screen_size;
271 info.screen_base = (char *)gd->fb_base;
273 memset(info.screen_base, 0, info.screen_size);
275 reset_total_layers();
276 div = dcu_set_pixel_clock(info.var.pixclock);
277 dcu_write32(®s->div_ratio, (div - 1));
279 dcu_write32(®s->disp_size,
280 DCU_DISP_SIZE_DELTA_Y(info.var.yres) |
281 DCU_DISP_SIZE_DELTA_X(info.var.xres / 16));
283 dcu_write32(®s->hsyn_para,
284 DCU_HSYN_PARA_BP(info.var.left_margin) |
285 DCU_HSYN_PARA_PW(info.var.hsync_len) |
286 DCU_HSYN_PARA_FP(info.var.right_margin));
288 dcu_write32(®s->vsyn_para,
289 DCU_VSYN_PARA_BP(info.var.upper_margin) |
290 DCU_VSYN_PARA_PW(info.var.vsync_len) |
291 DCU_VSYN_PARA_FP(info.var.lower_margin));
293 dcu_write32(®s->synpol,
294 DCU_SYN_POL_INV_PXCK_FALL |
295 DCU_SYN_POL_NEG_REMAIN |
296 DCU_SYN_POL_INV_VS_LOW |
297 DCU_SYN_POL_INV_HS_LOW);
299 dcu_write32(®s->bgnd,
300 DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0));
302 dcu_write32(®s->mode,
303 DCU_MODE_BLEND_ITER(DCU_LAYER_MAX_NUM) |
306 dcu_write32(®s->threshold,
307 DCU_THRESHOLD_LS_BF_VS(0x3) |
308 DCU_THRESHOLD_OUT_BUF_HIGH(0x78) |
309 DCU_THRESHOLD_OUT_BUF_LOW(0));
311 mode = dcu_read32(®s->mode);
312 dcu_write32(®s->mode, mode | DCU_MODE_NORMAL);
314 layer_ctrldesc_init(0, pixel_format);
319 ulong board_get_usable_ram_top(ulong total_size)
321 return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB;
324 void *video_hw_init(void)
326 static GraphicDevice ctfb;
328 unsigned int depth = 0, freq = 0;
329 struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
331 if (!video_get_video_mode(&ctfb.winSizeX, &ctfb.winSizeY, &depth, &freq,
335 /* Find the monitor port, which is a required option */
338 if (strncmp(options, "monitor=", 8) != 0)
341 switch (RESOLUTION(ctfb.winSizeX, ctfb.winSizeY)) {
342 case RESOLUTION(480, 272):
343 fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
345 case RESOLUTION(640, 480):
346 fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
349 printf("unsupported resolution %ux%u\n",
350 ctfb.winSizeX, ctfb.winSizeY);
353 info.var.xres = fsl_dcu_mode_db->xres;
354 info.var.yres = fsl_dcu_mode_db->yres;
355 info.var.bits_per_pixel = 32;
356 info.var.pixclock = fsl_dcu_mode_db->pixclock;
357 info.var.left_margin = fsl_dcu_mode_db->left_margin;
358 info.var.right_margin = fsl_dcu_mode_db->right_margin;
359 info.var.upper_margin = fsl_dcu_mode_db->upper_margin;
360 info.var.lower_margin = fsl_dcu_mode_db->lower_margin;
361 info.var.hsync_len = fsl_dcu_mode_db->hsync_len;
362 info.var.vsync_len = fsl_dcu_mode_db->vsync_len;
363 info.var.sync = fsl_dcu_mode_db->sync;
364 info.var.vmode = fsl_dcu_mode_db->vmode;
365 info.fix.line_length = info.var.xres * info.var.bits_per_pixel / 8;
367 if (platform_dcu_init(ctfb.winSizeX, ctfb.winSizeY,
368 options + 8, fsl_dcu_mode_db) < 0)
371 ctfb.frameAdrs = (unsigned int)info.screen_base;
372 ctfb.plnSizeX = ctfb.winSizeX;
373 ctfb.plnSizeY = ctfb.winSizeY;
376 ctfb.gdfIndex = GDF_32BIT_X888RGB;
378 ctfb.memSize = info.screen_size;
383 #if defined(CONFIG_OF_BOARD_SETUP)
384 int fsl_dcu_fixedfb_setup(void *blob)
389 start = gd->bd->bi_dram[0].start;
390 size = gd->bd->bi_dram[0].size - info.screen_size;
393 * Align size on section size (1 MiB).
396 ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
398 eprintf("Cannot setup fb: Error reserving memory\n");