2 * (C) Copyright 2001-2002
3 * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /************************************************************************/
26 /************************************************************************/
37 #include <linux/types.h>
38 #include <stdio_dev.h>
39 #if defined(CONFIG_POST)
46 /************************************************************************/
47 /* ** CONFIG STUFF -- should be moved to board config file */
48 /************************************************************************/
49 #ifndef CONFIG_LCD_INFO
50 #define CONFIG_LCD_INFO /* Display Logo, (C) and system info */
53 #if defined(CONFIG_V37) || defined(CONFIG_EDT32F10)
54 #undef CONFIG_LCD_LOGO
55 #undef CONFIG_LCD_INFO
58 /*----------------------------------------------------------------------*/
59 #ifdef CONFIG_KYOCERA_KCS057QV1AJ
61 * Kyocera KCS057QV1AJ-G23. Passive, color, single scan.
63 #define LCD_BPP LCD_COLOR4
65 vidinfo_t panel_info = {
66 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
67 LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0
68 /* wbl, vpw, lcdac, wbf */
70 #endif /* CONFIG_KYOCERA_KCS057QV1AJ */
71 /*----------------------------------------------------------------------*/
73 /*----------------------------------------------------------------------*/
74 #ifdef CONFIG_HITACHI_SP19X001_Z1A
76 * Hitachi SP19X001-. Active, color, single scan.
78 vidinfo_t panel_info = {
79 640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
80 LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0
81 /* wbl, vpw, lcdac, wbf */
83 #endif /* CONFIG_HITACHI_SP19X001_Z1A */
84 /*----------------------------------------------------------------------*/
86 /*----------------------------------------------------------------------*/
87 #ifdef CONFIG_NEC_NL6448AC33
89 * NEC NL6448AC33-18. Active, color, single scan.
91 vidinfo_t panel_info = {
92 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
93 3, 0, 0, 1, 1, 144, 2, 0, 33
94 /* wbl, vpw, lcdac, wbf */
96 #endif /* CONFIG_NEC_NL6448AC33 */
97 /*----------------------------------------------------------------------*/
99 #ifdef CONFIG_NEC_NL6448BC20
101 * NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan.
103 vidinfo_t panel_info = {
104 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
105 3, 0, 0, 1, 1, 144, 2, 0, 33
106 /* wbl, vpw, lcdac, wbf */
108 #endif /* CONFIG_NEC_NL6448BC20 */
109 /*----------------------------------------------------------------------*/
111 #ifdef CONFIG_NEC_NL6448BC33_54
113 * NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan.
115 vidinfo_t panel_info = {
116 640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
117 3, 0, 0, 1, 1, 144, 2, 0, 33
118 /* wbl, vpw, lcdac, wbf */
120 #endif /* CONFIG_NEC_NL6448BC33_54 */
121 /*----------------------------------------------------------------------*/
123 #ifdef CONFIG_SHARP_LQ104V7DS01
125 * SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
127 vidinfo_t panel_info = {
128 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
129 3, 0, 0, 1, 1, 25, 1, 0, 33
130 /* wbl, vpw, lcdac, wbf */
132 #endif /* CONFIG_SHARP_LQ104V7DS01 */
133 /*----------------------------------------------------------------------*/
135 #ifdef CONFIG_SHARP_16x9
137 * Sharp 320x240. Active, color, single scan. It isn't 16x9, and I am
138 * not sure what it is.......
140 vidinfo_t panel_info = {
141 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
142 3, 0, 0, 1, 1, 15, 4, 0, 3
144 #endif /* CONFIG_SHARP_16x9 */
145 /*----------------------------------------------------------------------*/
147 #ifdef CONFIG_SHARP_LQ057Q3DC02
149 * Sharp LQ057Q3DC02 display. Active, color, single scan.
154 vidinfo_t panel_info = {
155 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
156 3, 0, 0, 1, 1, 15, 4, 0, 3
157 /* wbl, vpw, lcdac, wbf */
159 #define CONFIG_LCD_INFO_BELOW_LOGO
160 #endif /* CONFIG_SHARP_LQ057Q3DC02 */
161 /*----------------------------------------------------------------------*/
163 #ifdef CONFIG_SHARP_LQ64D341
165 * Sharp LQ64D341 display, 640x480. Active, color, single scan.
167 vidinfo_t panel_info = {
168 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
169 3, 0, 0, 1, 1, 128, 16, 0, 32
170 /* wbl, vpw, lcdac, wbf */
172 #endif /* CONFIG_SHARP_LQ64D341 */
174 #ifdef CONFIG_SHARP_LQ065T9DR51U
176 * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan.
178 vidinfo_t panel_info = {
179 400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
180 3, 0, 0, 1, 1, 248, 4, 0, 35
181 /* wbl, vpw, lcdac, wbf */
183 #define CONFIG_LCD_INFO_BELOW_LOGO
184 #endif /* CONFIG_SHARP_LQ065T9DR51U */
186 #ifdef CONFIG_SHARP_LQ084V1DG21
188 * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan.
190 vidinfo_t panel_info = {
191 640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
192 3, 0, 0, 1, 1, 160, 3, 0, 48
193 /* wbl, vpw, lcdac, wbf */
195 #endif /* CONFIG_SHARP_LQ084V1DG21 */
197 /*----------------------------------------------------------------------*/
199 #ifdef CONFIG_HLD1045
201 * HLD1045 display, 640x480. Active, color, single scan.
203 vidinfo_t panel_info = {
204 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
205 3, 0, 0, 1, 1, 160, 3, 0, 48
206 /* wbl, vpw, lcdac, wbf */
208 #endif /* CONFIG_HLD1045 */
209 /*----------------------------------------------------------------------*/
211 #ifdef CONFIG_PRIMEVIEW_V16C6448AC
213 * Prime View V16C6448AC
215 vidinfo_t panel_info = {
216 640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
217 3, 0, 0, 1, 1, 144, 2, 0, 35
218 /* wbl, vpw, lcdac, wbf */
220 #endif /* CONFIG_PRIMEVIEW_V16C6448AC */
222 /*----------------------------------------------------------------------*/
224 #ifdef CONFIG_OPTREX_BW
226 * Optrex CBL50840-2 NF-FW 99 22 M5
228 * Hitachi LMG6912RPFC-00T
232 * 320x240. Black & white.
234 #define OPTREX_BPP 0 /* 0 - monochrome, 1 bpp */
235 /* 1 - 4 grey levels, 2 bpp */
236 /* 2 - 16 grey levels, 4 bpp */
237 vidinfo_t panel_info = {
238 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
239 OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4
241 #endif /* CONFIG_OPTREX_BW */
243 /*-----------------------------------------------------------------*/
244 #ifdef CONFIG_EDT32F10
246 * Emerging Display Technologies 320x240. Passive, monochrome, single scan.
248 #define LCD_BPP LCD_MONOCHROME
251 vidinfo_t panel_info = {
252 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
253 LCD_BPP, 0, 0, 0, 0, 33, 0, 0, 0
256 /*----------------------------------------------------------------------*/
260 * Frame buffer memory information
262 void *lcd_base; /* Start of framebuffer memory */
264 /************************************************************************/
266 void lcd_ctrl_init (void *lcdbase);
267 void lcd_enable (void);
268 #if LCD_BPP == LCD_COLOR8
269 void lcd_setcolreg (ushort regno,
270 ushort red, ushort green, ushort blue);
272 #if LCD_BPP == LCD_MONOCHROME
273 void lcd_initcolregs (void);
276 #if defined(CONFIG_RBC823)
277 void lcd_disable (void);
280 /************************************************************************/
282 /************************************************************************/
283 /* ----------------- chipset specific functions ----------------------- */
284 /************************************************************************/
287 * Calculate fb size for VIDEOLFB_ATAG.
289 ulong calc_fbsize (void)
292 int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
294 size = line_length * panel_info.vl_row;
299 void lcd_ctrl_init (void *lcdbase)
301 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
302 volatile lcd823_t *lcdp = &immr->im_lcd;
307 /* Initialize the LCD control register according to the LCD
308 * parameters defined. We do everything here but enable
312 #ifdef CONFIG_RPXLITE
313 /* This is special for RPXlite_DW Software Development Platform **[Sam]** */
314 panel_info.vl_dp = CONFIG_SYS_LOW;
317 lccrtmp = LCDBIT (LCCR_BNUM_BIT,
318 (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128));
320 lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp) |
321 LCDBIT (LCCR_OEP_BIT, panel_info.vl_oep) |
322 LCDBIT (LCCR_HSP_BIT, panel_info.vl_hsp) |
323 LCDBIT (LCCR_VSP_BIT, panel_info.vl_vsp) |
324 LCDBIT (LCCR_DP_BIT, panel_info.vl_dp) |
325 LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix) |
326 LCDBIT (LCCR_LBW_BIT, panel_info.vl_lbw) |
327 LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt) |
328 LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor) |
329 LCDBIT (LCCR_TFT_BIT, panel_info.vl_tft);
332 lccrtmp |= ((SIU_LEVEL5 / 2) << 12);
333 lccrtmp |= LCCR_EIEN;
336 lcdp->lcd_lccr = lccrtmp;
337 lcdp->lcd_lcsr = 0xFF; /* Clear pending interrupts */
339 /* Initialize LCD controller bus priorities.
342 immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) | 1; /* RAID = 01, LAID = 00 */
344 immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */
346 /* set SHFT/CLOCK division factor 4
347 * This needs to be set based upon display type and processor
348 * speed. The TFT displays run about 20 to 30 MHz.
349 * I was running 64 MHz processor speed.
350 * The value for this divider must be chosen so the result is
351 * an integer of the processor speed (i.e., divide by 3 with
352 * 64 MHz would be bad).
354 immr->im_clkrst.car_sccr &= ~0x1F;
355 immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */
357 #endif /* CONFIG_RBC823 */
359 #if defined(CONFIG_RBC823)
360 /* Enable LCD on port D.
362 immr->im_ioport.iop_pddat &= 0x0300;
363 immr->im_ioport.iop_pdpar |= 0x1CFF;
364 immr->im_ioport.iop_pddir |= 0x1CFF;
366 /* Configure LCD_ON, VEE_ON, CCFL_ON on port B.
368 immr->im_cpm.cp_pbdat &= ~0x00005001;
369 immr->im_cpm.cp_pbpar &= ~0x00005001;
370 immr->im_cpm.cp_pbdir |= 0x00005001;
371 #elif !defined(CONFIG_EDT32F10)
372 /* Enable LCD on port D.
374 immr->im_ioport.iop_pdpar |= 0x1FFF;
375 immr->im_ioport.iop_pddir |= 0x1FFF;
377 /* Enable LCD_A/B/C on port B.
379 immr->im_cpm.cp_pbpar |= 0x00005001;
380 immr->im_cpm.cp_pbdir |= 0x00005001;
382 /* Enable LCD on port D.
384 immr->im_ioport.iop_pdpar |= 0x1DFF;
385 immr->im_ioport.iop_pdpar &= ~0x0200;
386 immr->im_ioport.iop_pddir |= 0x1FFF;
387 immr->im_ioport.iop_pddat |= 0x0200;
390 /* Load the physical address of the linear frame buffer
391 * into the LCD controller.
392 * BIG NOTE: This has to be modified to load A and B depending
393 * upon the split mode of the LCD.
395 lcdp->lcd_lcfaa = (ulong)lcd_base;
396 lcdp->lcd_lcfba = (ulong)lcd_base;
398 /* MORE HACKS...This must be updated according to 823 manual
399 * for different panels.
400 * Udi Finkelstein - done - see below:
401 * Note: You better not try unsupported combinations such as
402 * 4-bit wide passive dual scan LCD at 4/8 Bit color.
406 (panel_info.vl_tft ? 8 :
407 (((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */
408 /* use << to mult by: single scan = 1, dual scan = 2 */
409 panel_info.vl_splt) *
410 (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */
412 lcdp->lcd_lchcr = LCHCR_BO |
413 LCDBIT (LCHCR_AT_BIT, 4) |
414 LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) |
417 lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) |
418 LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) |
419 LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) |
424 /*----------------------------------------------------------------------*/
426 #ifdef NOT_USED_SO_FAR
428 lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue)
430 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
431 volatile cpm8xx_t *cp = &(immr->im_cpm);
432 unsigned short colreg, *cmap_ptr;
434 cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];
437 #ifdef CONFIG_SYS_INVERT_COLORS
441 *red = (colreg >> 8) & 0x0F;
442 *green = (colreg >> 4) & 0x0F;
443 *blue = colreg & 0x0F;
445 #endif /* NOT_USED_SO_FAR */
447 /*----------------------------------------------------------------------*/
449 #if LCD_BPP == LCD_COLOR8
451 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
453 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
454 volatile cpm8xx_t *cp = &(immr->im_cpm);
455 unsigned short colreg, *cmap_ptr;
457 cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];
459 colreg = ((red & 0x0F) << 8) |
460 ((green & 0x0F) << 4) |
462 #ifdef CONFIG_SYS_INVERT_COLORS
467 debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n",
468 regno, &(cp->lcd_cmap[regno * 2]),
470 cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]);
472 #endif /* LCD_COLOR8 */
474 /*----------------------------------------------------------------------*/
476 #if LCD_BPP == LCD_MONOCHROME
478 void lcd_initcolregs (void)
480 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
481 volatile cpm8xx_t *cp = &(immr->im_cpm);
484 for (regno = 0; regno < 16; regno++) {
485 cp->lcd_cmap[regno * 2] = 0;
486 cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f;
491 /*----------------------------------------------------------------------*/
493 void lcd_enable (void)
495 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
496 volatile lcd823_t *lcdp = &immr->im_lcd;
498 /* Enable the LCD panel */
499 #ifndef CONFIG_RBC823
500 immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */
502 lcdp->lcd_lccr |= LCCR_PON;
505 /* Turn on display backlight */
506 immr->im_cpm.cp_pbpar |= 0x00008000;
507 immr->im_cpm.cp_pbdir |= 0x00008000;
508 #elif defined(CONFIG_RBC823)
509 /* Turn on display backlight */
510 immr->im_cpm.cp_pbdat |= 0x00004000;
513 #if defined(CONFIG_LWMON)
514 { uchar c = pic_read (0x60);
515 #if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON)
516 /* Enable LCD later in sysmon test, only if temperature is OK */
518 c |= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */
522 #endif /* CONFIG_LWMON */
524 #if defined(CONFIG_R360MPI)
526 extern void r360_i2c_lcd_write (uchar data0, uchar data1);
527 unsigned long bgi, ctr;
530 if ((p = getenv("lcdbgi")) != NULL) {
531 bgi = simple_strtoul (p, 0, 10) & 0xFFF;
536 if ((p = getenv("lcdctr")) != NULL) {
537 ctr = simple_strtoul (p, 0, 10) & 0xFFF;
542 r360_i2c_lcd_write(0x10, 0x01);
543 r360_i2c_lcd_write(0x20, 0x01);
544 r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF);
545 r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF);
547 #endif /* CONFIG_R360MPI */
549 udelay(200000); /* wait 200ms */
550 /* Turn VEE_ON first */
551 immr->im_cpm.cp_pbdat |= 0x00000001;
552 udelay(200000); /* wait 200ms */
553 /* Now turn on LCD_ON */
554 immr->im_cpm.cp_pbdat |= 0x00001000;
556 #ifdef CONFIG_RRVISION
557 debug ("PC4->Output(1): enable LVDS\n");
558 debug ("PC5->Output(0): disable PAL clock\n");
559 immr->im_ioport.iop_pddir |= 0x1000;
560 immr->im_ioport.iop_pcpar &= ~(0x0C00);
561 immr->im_ioport.iop_pcdir |= 0x0C00 ;
562 immr->im_ioport.iop_pcdat |= 0x0800 ;
563 immr->im_ioport.iop_pcdat &= ~(0x0400);
564 debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n",
565 immr->im_ioport.iop_pdpar,
566 immr->im_ioport.iop_pddir,
567 immr->im_ioport.iop_pddat);
568 debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n",
569 immr->im_ioport.iop_pcpar,
570 immr->im_ioport.iop_pcdir,
571 immr->im_ioport.iop_pcdat);
575 /*----------------------------------------------------------------------*/
577 #if defined (CONFIG_RBC823)
578 void lcd_disable (void)
580 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
581 volatile lcd823_t *lcdp = &immr->im_lcd;
583 #if defined(CONFIG_LWMON)
584 { uchar c = pic_read (0x60);
585 c &= ~0x07; /* Power off CCFL, Disable CCFL, Chip Disable LCD */
588 #elif defined(CONFIG_R360MPI)
590 extern void r360_i2c_lcd_write (uchar data0, uchar data1);
592 r360_i2c_lcd_write(0x10, 0x00);
593 r360_i2c_lcd_write(0x20, 0x00);
594 r360_i2c_lcd_write(0x30, 0x00);
595 r360_i2c_lcd_write(0x40, 0x00);
597 #endif /* CONFIG_LWMON */
598 /* Disable the LCD panel */
599 lcdp->lcd_lccr &= ~LCCR_PON;
601 /* Turn off display backlight, VEE and LCD_ON */
602 immr->im_cpm.cp_pbdat &= ~0x00005001;
604 immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25)); /* LAM = 0 */
605 #endif /* CONFIG_RBC823 */
607 #endif /* NOT_USED_SO_FAR || CONFIG_RBC823 */
610 /************************************************************************/
612 #endif /* CONFIG_LCD */