4 * (C) Copyright 2017 Vasily Khoruzhick <anarsoul@gmail.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <video_bridge.h>
12 #include <backlight.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/lcdc.h>
18 #include <asm/arch/gpio.h>
21 struct sunxi_lcd_priv {
22 struct display_timing timing;
26 static void sunxi_lcdc_config_pinmux(void)
28 #ifdef CONFIG_MACH_SUN50I
31 for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(21); pin++) {
32 sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
33 sunxi_gpio_set_drv(pin, 3);
38 static int sunxi_lcd_enable(struct udevice *dev, int bpp,
39 const struct display_timing *edid)
41 struct sunxi_ccm_reg * const ccm =
42 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
43 struct sunxi_lcdc_reg * const lcdc =
44 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
45 struct sunxi_lcd_priv *priv = dev_get_priv(dev);
46 struct udevice *backlight;
47 int clk_div, clk_double, ret;
50 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
52 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
55 sunxi_lcdc_config_pinmux();
56 lcdc_pll_set(ccm, 0, edid->pixelclock.typ / 1000,
57 &clk_div, &clk_double, false);
58 lcdc_tcon0_mode_set(lcdc, edid, clk_div, false,
59 priv->panel_bpp, CONFIG_VIDEO_LCD_DCLK_PHASE);
60 lcdc_enable(lcdc, priv->panel_bpp);
62 ret = uclass_get_device(UCLASS_PANEL_BACKLIGHT, 0, &backlight);
64 backlight_enable(backlight);
69 static int sunxi_lcd_read_timing(struct udevice *dev,
70 struct display_timing *timing)
72 struct sunxi_lcd_priv *priv = dev_get_priv(dev);
74 memcpy(timing, &priv->timing, sizeof(struct display_timing));
79 static int sunxi_lcd_probe(struct udevice *dev)
82 struct sunxi_lcd_priv *priv = dev_get_priv(dev);
84 int node, timing_node, val;
86 #ifdef CONFIG_VIDEO_BRIDGE
87 /* Try to get timings from bridge first */
88 ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &cdev);
93 ret = video_bridge_attach(cdev);
95 debug("video bridge attach failed: %d\n", ret);
98 ret = video_bridge_read_edid(cdev, edid, EDID_SIZE);
100 ret = edid_get_timing(edid, ret,
101 &priv->timing, &channel_bpp);
102 priv->panel_bpp = channel_bpp * 3;
109 /* Fallback to timings from DT if there's no bridge or
110 * if reading EDID failed
112 ret = uclass_get_device(UCLASS_PANEL, 0, &cdev);
114 debug("video panel not found: %d\n", ret);
118 if (fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(cdev),
120 debug("%s: Failed to decode display timing\n", __func__);
123 timing_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(cdev),
125 node = fdt_first_subnode(gd->fdt_blob, timing_node);
126 val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1);
128 priv->panel_bpp = val;
130 priv->panel_bpp = 18;
135 static const struct dm_display_ops sunxi_lcd_ops = {
136 .read_timing = sunxi_lcd_read_timing,
137 .enable = sunxi_lcd_enable,
140 U_BOOT_DRIVER(sunxi_lcd) = {
142 .id = UCLASS_DISPLAY,
143 .ops = &sunxi_lcd_ops,
144 .probe = sunxi_lcd_probe,
145 .priv_auto_alloc_size = sizeof(struct sunxi_lcd_priv),
148 #ifdef CONFIG_MACH_SUN50I
149 U_BOOT_DEVICE(sunxi_lcd) = {