2 * Copyright (c) 2011 The Chromium OS Authors.
3 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/system.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/funcmux.h>
16 #include <asm/arch/pinmux.h>
17 #include <asm/arch/pwm.h>
18 #include <asm/arch/display.h>
19 #include <asm/arch-tegra/timer.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 /* These are the stages we go throuh in enabling the LCD */
34 static enum stage_t stage; /* Current stage we are at */
35 static unsigned long timer_next; /* Time we can move onto next stage */
37 /* Our LCD config, set up in handle_stage() */
38 static struct fdt_panel_config config;
39 struct fdt_disp_config *disp_config; /* Display controller config */
40 static struct fdt_disp_config dconfig;
43 /* Maximum LCD size we support */
46 LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */
49 vidinfo_t panel_info = {
50 /* Insert a value here so that we don't end up in the BSS */
54 static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
56 unsigned h_dda, v_dda;
59 val = readl(&dc->cmd.disp_win_header);
60 val |= WINDOW_A_SELECT;
61 writel(val, &dc->cmd.disp_win_header);
63 writel(win->fmt, &dc->win.color_depth);
65 clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
66 BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
68 val = win->out_x << H_POSITION_SHIFT;
69 val |= win->out_y << V_POSITION_SHIFT;
70 writel(val, &dc->win.pos);
72 val = win->out_w << H_SIZE_SHIFT;
73 val |= win->out_h << V_SIZE_SHIFT;
74 writel(val, &dc->win.size);
76 val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
77 val |= win->h << V_PRESCALED_SIZE_SHIFT;
78 writel(val, &dc->win.prescaled_size);
80 writel(0, &dc->win.h_initial_dda);
81 writel(0, &dc->win.v_initial_dda);
83 h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
84 v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
86 val = h_dda << H_DDA_INC_SHIFT;
87 val |= v_dda << V_DDA_INC_SHIFT;
88 writel(val, &dc->win.dda_increment);
90 writel(win->stride, &dc->win.line_stride);
91 writel(0, &dc->win.buf_stride);
96 writel(val, &dc->win.win_opt);
98 writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
99 writel(win->x, &dc->winbuf.addr_h_offset);
100 writel(win->y, &dc->winbuf.addr_v_offset);
102 writel(0xff00, &dc->win.blend_nokey);
103 writel(0xff00, &dc->win.blend_1win);
105 val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
106 val |= GENERAL_UPDATE | WIN_A_UPDATE;
107 writel(val, &dc->cmd.state_ctrl);
110 static void write_pair(struct fdt_disp_config *config, int item, u32 *reg)
112 writel(config->horiz_timing[item] |
113 (config->vert_timing[item] << 16), reg);
116 static int update_display_mode(struct dc_disp_reg *disp,
117 struct fdt_disp_config *config)
123 writel(0x0, &disp->disp_timing_opt);
124 write_pair(config, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync);
125 write_pair(config, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width);
126 write_pair(config, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch);
127 write_pair(config, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch);
129 writel(config->width | (config->height << 16), &disp->disp_active);
131 val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
132 val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
133 writel(val, &disp->data_enable_opt);
135 val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
136 val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
137 val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
138 writel(val, &disp->disp_interface_ctrl);
141 * The pixel clock divider is in 7.1 format (where the bottom bit
142 * represents 0.5). Here we calculate the divider needed to get from
143 * the display clock (typically 600MHz) to the pixel clock. We round
144 * up or down as requried.
146 rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
147 div = ((rate * 2 + config->pixel_clock / 2) / config->pixel_clock) - 2;
148 debug("Display clock %lu, divider %lu\n", rate, div);
150 writel(0x00010001, &disp->shift_clk_opt);
152 val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
153 val |= div << SHIFT_CLK_DIVIDER_SHIFT;
154 writel(val, &disp->disp_clk_ctrl);
159 /* Start up the display and turn on power to PWMs */
160 static void basic_init(struct dc_cmd_reg *cmd)
164 writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
165 writel(0x0000011a, &cmd->cont_syncpt_vsync);
166 writel(0x00000000, &cmd->int_type);
167 writel(0x00000000, &cmd->int_polarity);
168 writel(0x00000000, &cmd->int_mask);
169 writel(0x00000000, &cmd->int_enb);
171 val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
172 val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
174 writel(val, &cmd->disp_pow_ctrl);
176 val = readl(&cmd->disp_cmd);
177 val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
178 writel(val, &cmd->disp_cmd);
181 static void basic_init_timer(struct dc_disp_reg *disp)
183 writel(0x00000020, &disp->mem_high_pri);
184 writel(0x00000001, &disp->mem_high_pri_timer);
187 static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
194 static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
201 static const u32 rgb_data_tab[PIN_REG_COUNT] = {
208 static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
218 static void rgb_enable(struct dc_com_reg *com)
222 for (i = 0; i < PIN_REG_COUNT; i++) {
223 writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
224 writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
225 writel(rgb_data_tab[i], &com->pin_output_data[i]);
228 for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
229 writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
232 static int setup_window(struct disp_ctl_win *win,
233 struct fdt_disp_config *config)
237 win->w = config->width;
238 win->h = config->height;
241 win->out_w = config->width;
242 win->out_h = config->height;
243 win->phys_addr = config->frame_buffer;
244 win->stride = config->width * (1 << config->log2_bpp) / 8;
245 debug("%s: depth = %d\n", __func__, config->log2_bpp);
246 switch (config->log2_bpp) {
249 win->fmt = COLOR_DEPTH_R8G8B8A8;
253 win->fmt = COLOR_DEPTH_B5G6R5;
258 debug("Unsupported LCD bit depth");
266 * Return the current display configuration
268 * @return pointer to display configuration, or NULL if there is no valid
271 struct fdt_disp_config *tegra_display_get_config(void)
273 return dconfig.valid ? &dconfig : NULL;
276 static void debug_timing(const char *name, unsigned int timing[])
281 debug("%s timing: ", name);
282 for (i = 0; i < FDT_LCD_TIMING_COUNT; i++)
283 debug("%d ", timing[i]);
289 * Decode panel information from the fdt, according to a standard binding
291 * @param blob fdt blob
292 * @param node offset of fdt node to read from
293 * @param config structure to store fdt config into
294 * @return 0 if ok, -ve on error
296 static int tegra_decode_panel(const void *blob, int node,
297 struct fdt_disp_config *config)
299 int front, back, ref;
301 config->width = fdtdec_get_int(blob, node, "xres", -1);
302 config->height = fdtdec_get_int(blob, node, "yres", -1);
303 config->pixel_clock = fdtdec_get_int(blob, node, "clock", 0);
304 if (!config->pixel_clock || config->width == -1 ||
305 config->height == -1) {
306 debug("%s: Pixel parameters missing\n", __func__);
307 return -FDT_ERR_NOTFOUND;
310 back = fdtdec_get_int(blob, node, "left-margin", -1);
311 front = fdtdec_get_int(blob, node, "right-margin", -1);
312 ref = fdtdec_get_int(blob, node, "hsync-len", -1);
313 if ((back | front | ref) == -1) {
314 debug("%s: Horizontal parameters missing\n", __func__);
315 return -FDT_ERR_NOTFOUND;
318 /* Use a ref-to-sync of 1 always, and take this from the front porch */
319 config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
320 config->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
321 config->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
322 config->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
323 config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC];
324 debug_timing("horiz", config->horiz_timing);
326 back = fdtdec_get_int(blob, node, "upper-margin", -1);
327 front = fdtdec_get_int(blob, node, "lower-margin", -1);
328 ref = fdtdec_get_int(blob, node, "vsync-len", -1);
329 if ((back | front | ref) == -1) {
330 debug("%s: Vertical parameters missing\n", __func__);
331 return -FDT_ERR_NOTFOUND;
334 config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
335 config->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
336 config->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
337 config->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
338 config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC];
339 debug_timing("vert", config->vert_timing);
345 * Decode the display controller information from the fdt.
347 * @param blob fdt blob
348 * @param config structure to store fdt config into
349 * @return 0 if ok, -ve on error
351 static int tegra_display_decode_config(const void *blob,
352 struct fdt_disp_config *config)
357 /* TODO: Support multiple controllers */
358 node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_DC);
360 debug("%s: Cannot find display controller node in fdt\n",
364 config->disp = (struct disp_ctlr *)fdtdec_get_addr(blob, node, "reg");
366 debug("%s: No display controller address\n", __func__);
370 rgb = fdt_subnode_offset(blob, node, "rgb");
372 config->panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
373 if (config->panel_node < 0) {
374 debug("%s: Cannot find panel information\n", __func__);
378 if (tegra_decode_panel(blob, config->panel_node, config)) {
379 debug("%s: Failed to decode panel information\n", __func__);
383 bpp = fdtdec_get_int(blob, config->panel_node, "nvidia,bits-per-pixel",
386 if (bpp == (1 << bit))
387 config->log2_bpp = bit;
389 config->log2_bpp = bpp;
391 debug("%s: Pixel bpp parameters missing\n", __func__);
392 return -FDT_ERR_NOTFOUND;
396 config->valid = 1; /* we have a valid configuration */
402 * Register a new display based on device tree configuration.
404 * The frame buffer can be positioned by U-Boot or overriden by the fdt.
405 * You should pass in the U-Boot address here, and check the contents of
406 * struct fdt_disp_config to see what was actually chosen.
408 * @param blob Device tree blob
409 * @param default_lcd_base Default address of LCD frame buffer
410 * @return 0 if ok, -1 on error (unsupported bits per pixel)
412 static int tegra_display_probe(const void *blob, void *default_lcd_base)
414 struct disp_ctl_win window;
417 if (tegra_display_decode_config(blob, &dconfig))
420 dconfig.frame_buffer = (u32)default_lcd_base;
422 dc = (struct dc_ctlr *)dconfig.disp;
425 * A header file for clock constants was NAKed upstream.
426 * TODO: Put this into the FDT and fdt_lcd struct when we have clock
429 clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
431 clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
433 basic_init(&dc->cmd);
434 basic_init_timer(&dc->disp);
435 rgb_enable(&dc->com);
437 if (dconfig.pixel_clock)
438 update_display_mode(&dc->disp, &dconfig);
440 if (setup_window(&window, &dconfig))
443 update_window(dc, &window);
448 static void update_panel_size(struct fdt_disp_config *config)
450 panel_info.vl_col = config->width;
451 panel_info.vl_row = config->height;
452 panel_info.vl_bpix = config->log2_bpp;
456 * Main init function called by lcd driver.
457 * Inits and then prints test pattern if required.
460 void lcd_ctrl_init(void *lcdbase)
462 int type = DCACHE_OFF;
467 /* Make sure that we can acommodate the selected LCD */
468 assert(disp_config->width <= LCD_MAX_WIDTH);
469 assert(disp_config->height <= LCD_MAX_HEIGHT);
470 assert(disp_config->log2_bpp <= LCD_MAX_LOG2_BPP);
471 if (disp_config->width <= LCD_MAX_WIDTH
472 && disp_config->height <= LCD_MAX_HEIGHT
473 && disp_config->log2_bpp <= LCD_MAX_LOG2_BPP)
474 update_panel_size(disp_config);
475 size = lcd_get_size(&lcd_line_length);
477 /* Set up the LCD caching as requested */
478 if (config.cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
479 type = DCACHE_WRITETHROUGH;
480 else if (config.cache_type & FDT_LCD_CACHE_WRITE_BACK)
481 type = DCACHE_WRITEBACK;
482 mmu_set_region_dcache_behaviour(disp_config->frame_buffer, size, type);
484 /* Enable flushing after LCD writes if requested */
485 lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH);
487 debug("LCD frame buffer at %pa\n", &disp_config->frame_buffer);
490 ulong calc_fbsize(void)
492 return (panel_info.vl_col * panel_info.vl_row *
493 NBITS(panel_info.vl_bpix)) / 8;
496 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
500 void tegra_lcd_early_init(const void *blob)
503 * Go with the maximum size for now. We will fix this up after
504 * relocation. These values are only used for memory alocation.
506 panel_info.vl_col = LCD_MAX_WIDTH;
507 panel_info.vl_row = LCD_MAX_HEIGHT;
508 panel_info.vl_bpix = LCD_MAX_LOG2_BPP;
512 * Decode the panel information from the fdt.
514 * @param blob fdt blob
515 * @param config structure to store fdt config into
516 * @return 0 if ok, -ve on error
518 static int fdt_decode_lcd(const void *blob, struct fdt_panel_config *config)
522 disp_config = tegra_display_get_config();
524 debug("%s: Display controller is not configured\n", __func__);
527 display_node = disp_config->panel_node;
528 if (display_node < 0) {
529 debug("%s: No panel configuration available\n", __func__);
533 config->pwm_channel = pwm_request(blob, display_node, "nvidia,pwm");
534 if (config->pwm_channel < 0) {
535 debug("%s: Unable to request PWM channel\n", __func__);
539 config->cache_type = fdtdec_get_int(blob, display_node,
541 FDT_LCD_CACHE_WRITE_BACK_FLUSH);
543 /* These GPIOs are all optional */
544 gpio_request_by_name_nodev(blob, display_node,
545 "nvidia,backlight-enable-gpios", 0,
546 &config->backlight_en, GPIOD_IS_OUT);
547 gpio_request_by_name_nodev(blob, display_node,
548 "nvidia,lvds-shutdown-gpios", 0,
549 &config->lvds_shutdown, GPIOD_IS_OUT);
550 gpio_request_by_name_nodev(blob, display_node,
551 "nvidia,backlight-vdd-gpios", 0,
552 &config->backlight_vdd, GPIOD_IS_OUT);
553 gpio_request_by_name_nodev(blob, display_node,
554 "nvidia,panel-vdd-gpios", 0,
555 &config->panel_vdd, GPIOD_IS_OUT);
557 return fdtdec_get_int_array(blob, display_node, "nvidia,panel-timings",
558 config->panel_timings, FDT_LCD_TIMINGS);
562 * Handle the next stage of device init
564 static int handle_stage(const void *blob)
566 debug("%s: stage %d\n", __func__, stage);
568 /* do the things for this stage */
571 /* Initialize the Tegra display controller */
572 if (tegra_display_probe(gd->fdt_blob, (void *)gd->fb_base)) {
573 printf("%s: Failed to probe display driver\n",
578 /* get panel details */
579 if (fdt_decode_lcd(blob, &config)) {
580 printf("No valid LCD information in device tree\n");
585 * It is possible that the FDT has requested that the LCD be
586 * disabled. We currently don't support this. It would require
587 * changes to U-Boot LCD subsystem to have LCD support
588 * compiled in but not used. An easier option might be to
589 * still have a frame buffer, but leave the backlight off and
590 * remove all mention of lcd in the stdout environment
594 funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
596 case STAGE_PANEL_VDD:
597 if (dm_gpio_is_valid(&config.panel_vdd))
598 dm_gpio_set_value(&config.panel_vdd, 1);
601 if (dm_gpio_is_valid(&config.lvds_shutdown))
602 dm_gpio_set_value(&config.lvds_shutdown, 1);
604 case STAGE_BACKLIGHT_VDD:
605 if (dm_gpio_is_valid(&config.backlight_vdd))
606 dm_gpio_set_value(&config.backlight_vdd, 1);
609 /* Enable PWM at 15/16 high, 32768 Hz with divider 1 */
610 pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
611 pinmux_tristate_disable(PMUX_PINGRP_GPU);
613 pwm_enable(config.pwm_channel, 32768, 0xdf, 1);
615 case STAGE_BACKLIGHT_EN:
616 if (dm_gpio_is_valid(&config.backlight_en))
617 dm_gpio_set_value(&config.backlight_en, 1);
623 /* set up timer for next stage */
624 timer_next = timer_get_us();
625 if (stage < FDT_LCD_TIMINGS)
626 timer_next += config.panel_timings[stage] * 1000;
628 /* move to next stage */
633 int tegra_lcd_check_next_stage(const void *blob, int wait)
635 if (stage == STAGE_DONE)
639 /* wait if we need to */
640 debug("%s: stage %d\n", __func__, stage);
641 if (stage != STAGE_START) {
642 int delay = timer_next - timer_get_us();
652 if (handle_stage(blob))
654 } while (wait && stage != STAGE_DONE);
655 if (stage == STAGE_DONE)
656 debug("%s: LCD init complete\n", __func__);
661 void lcd_enable(void)
664 * Backlight and power init will be done separately in
665 * tegra_lcd_check_next_stage(), which should be called in
668 * U-Boot code supports only colour depth, selected at compile time.
669 * The device tree setting should match this. Otherwise the display
670 * will not look right, and U-Boot may crash.
672 if (disp_config->log2_bpp != LCD_BPP) {
673 printf("%s: Error: LCD depth configured in FDT (%d = %dbpp)"
674 " must match setting of LCD_BPP (%d)\n", __func__,
675 disp_config->log2_bpp, disp_config->bpp, LCD_BPP);