1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
44 static u8 output_value = 0x0;
45 static int dev_mem_fd;
46 static void *gpio_controller;
47 static volatile u8 *gpio_data_register;
48 static volatile u8 *gpio_data_direction_register;
50 /* low level command set
52 int ep93xx_read(void);
53 void ep93xx_write(int tck, int tms, int tdi);
54 void ep93xx_reset(int trst, int srst);
56 int ep93xx_speed(int speed);
57 int ep93xx_register_commands(struct command_context_s *cmd_ctx);
58 int ep93xx_init(void);
59 int ep93xx_quit(void);
61 struct timespec ep93xx_zzzz;
63 jtag_interface_t ep93xx_interface =
67 .execute_queue = bitbang_execute_queue,
69 .speed = ep93xx_speed,
70 .register_commands = ep93xx_register_commands,
75 bitbang_interface_t ep93xx_bitbang =
78 .write = ep93xx_write,
79 .reset = ep93xx_reset,
85 return !!(*gpio_data_register & TDO_BIT);
88 void ep93xx_write(int tck, int tms, int tdi)
91 output_value |= TCK_BIT;
93 output_value &= TCK_BIT;
96 output_value |= TMS_BIT;
98 output_value &= TMS_BIT;
101 output_value |= TDI_BIT;
103 output_value &= TDI_BIT;
105 *gpio_data_register = output_value;
106 nanosleep(ep93xx_zzzz);
109 /* (1) assert or (0) deassert reset lines */
110 void ep93xx_reset(int trst, int srst)
113 output_value |= TRST_BIT;
115 output_value &= TRST_BIT;
118 output_value |= SRST_BIT;
120 output_value &= SRST_BIT;
122 *gpio_data_register = output_value;
123 nanosleep(ep93xx_zzzz);
126 int ep93xx_speed(int speed)
132 int ep93xx_register_commands(struct command_context_s *cmd_ctx)
138 static int set_gonk_mode(void)
143 syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
144 MAP_SHARED, dev_mem_fd, 0x80930000);
145 if (syscon == MAP_FAILED) {
147 return ERROR_JTAG_INIT_FAILED;
150 devicecfg = *((volatile int *)(syscon + 0x80));
151 *((volatile int *)(syscon + 0xc0)) = 0xaa;
152 *((volatile int *)(syscon + 0x80)) = devicecfg | 0x08000000;
154 munmap(syscon, 4096);
159 int ep93xx_init(void)
163 bitbang_interface = &ep93xx_bitbang;
165 ep93xx_zzzz.tv_sec = 0;
166 ep93xx_zzzz.tv_nsec = 10000000;
168 dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
169 if (dev_mem_fd < 0) {
171 return ERROR_JTAG_INIT_FAILED;
174 gpio_controller = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
175 MAP_SHARED, dev_mem_fd, 0x80840000);
176 if (gpio_controller == MAP_FAILED) {
179 return ERROR_JTAG_INIT_FAILED;
182 ret = set_gonk_mode();
183 if (ret != ERROR_OK) {
184 munmap(gpio_controller, 4096);
190 /* Use GPIO port A. */
191 gpio_data_register = gpio_controller + 0x00;
192 gpio_data_direction_register = gpio_controller + 0x10;
195 /* Use GPIO port B. */
196 gpio_data_register = gpio_controller + 0x04;
197 gpio_data_direction_register = gpio_controller + 0x14;
199 /* Use GPIO port C. */
200 gpio_data_register = gpio_controller + 0x08;
201 gpio_data_direction_register = gpio_controller + 0x18;
203 /* Use GPIO port D. */
204 gpio_data_register = gpio_controller + 0x0c;
205 gpio_data_direction_register = gpio_controller + 0x1c;
208 /* Use GPIO port C. */
209 gpio_data_register = gpio_controller + 0x08;
210 gpio_data_direction_register = gpio_controller + 0x18;
212 INFO("gpio_data_register = %p\n", gpio_data_register);
213 INFO("gpio_data_direction_reg = %p\n", gpio_data_direction_register);
215 * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
216 * TMS, TRST, SRST) as outputs. Drive TDI and TCK low, and
217 * TMS/TRST/SRST high.
219 output_value = TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
220 *gpio_data_register = output_value;
221 nanosleep(ep93xx_zzzz);
224 * Configure the direction register. 1 = output, 0 = input.
226 *gpio_data_direction_register =
227 TDI_BIT | TCK_BIT | TMS_BIT | TRST_BIT | SRST_BIT | VCC_BIT;
229 nanosleep(ep93xx_zzzz);
233 int ep93xx_quit(void)