git.sur5r.net Git - u-boot/blob - eth_t102xrdb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  *
   5  * Shengzhou Liu <Shengzhou.Liu@freescale.com>
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <netdev.h>
  11 #include <asm/mmu.h>
  12 #include <asm/processor.h>
  13 #include <asm/immap_85xx.h>
  14 #include <asm/fsl_law.h>
  15 #include <asm/fsl_serdes.h>
  16 #include <asm/fsl_portals.h>
  17 #include <asm/fsl_liodn.h>
  18 #include <malloc.h>
  19 #include <fm_eth.h>
  20 #include <fsl_mdio.h>
  21 #include <miiphy.h>
  22 #include <phy.h>
  23 #include <fsl_dtsec.h>
  24 #include <asm/fsl_serdes.h>
  25 #include "../common/fman.h"
  26
  27 int board_eth_init(bd_t *bis)
  28 {
  29 #if defined(CONFIG_FMAN_ENET)
  30         int i, interface;
  31         struct memac_mdio_info dtsec_mdio_info;
  32         struct memac_mdio_info tgec_mdio_info;
  33         struct mii_dev *dev;
  34         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  35         u32 srds_s1;
  36
  37         srds_s1 = in_be32(&gur->rcwsr[4]) &
  38                                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  39         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  40
  41         dtsec_mdio_info.regs =
  42                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  43
  44         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  45
  46         /* Register the 1G MDIO bus */
  47         fm_memac_mdio_init(bis, &dtsec_mdio_info);
  48
  49         tgec_mdio_info.regs =
  50                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  51         tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  52
  53         /* Register the 10G MDIO bus */
  54         fm_memac_mdio_init(bis, &tgec_mdio_info);
  55
  56         /* Set the on-board RGMII PHY address */
  57         fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
  58
  59         switch (srds_s1) {
  60 #ifdef CONFIG_TARGET_T1024RDB
  61         case 0x95:
  62                 /* set the on-board RGMII2  PHY */
  63                 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
  64
  65                 /* set 10G XFI with Aquantia AQR105 PHY */
  66                 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
  67                 break;
  68 #endif
  69         case 0x6a:
  70         case 0x6b:
  71         case 0x77:
  72         case 0x135:
  73                 /* set the on-board 2.5G SGMII AQR105 PHY */
  74                 fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
  75 #ifdef CONFIG_TARGET_T1023RDB
  76                 /* set the on-board 1G SGMII RTL8211F PHY */
  77                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
  78 #endif
  79                 break;
  80         default:
  81                 printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
  82                        srds_s1);
  83                 break;
  84         }
  85
  86         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  87                 interface = fm_info_get_enet_if(i);
  88                 switch (interface) {
  89                 case PHY_INTERFACE_MODE_RGMII:
  90                         dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  91                         fm_info_set_mdio(i, dev);
  92                         break;
  93                 case PHY_INTERFACE_MODE_SGMII:
  94 #if defined(CONFIG_TARGET_T1023RDB)
  95                         dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  96 #elif defined(CONFIG_TARGET_T1024RDB)
  97                         dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
  98 #endif
  99                         fm_info_set_mdio(i, dev);
 100                         break;
 101                 case PHY_INTERFACE_MODE_SGMII_2500:
 102                         dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
 103                         fm_info_set_mdio(i, dev);
 104                         break;
 105                 default:
 106                         break;
 107                 }
 108         }
 109
 110         for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 111                 switch (fm_info_get_enet_if(i)) {
 112                 case PHY_INTERFACE_MODE_XGMII:
 113                         dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
 114                         fm_info_set_mdio(i, dev);
 115                         break;
 116                 default:
 117                         break;
 118                 }
 119         }
 120
 121         cpu_eth_init(bis);
 122 #endif /* CONFIG_FMAN_ENET */
 123
 124         return pci_eth_init(bis);
 125 }
 126
 127 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 128                               enum fm_port port, int offset)
 129 {
 130 #if defined(CONFIG_TARGET_T1024RDB)
 131         if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
 132              (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
 133                         (port == FM1_DTSEC3)) {
 134                 fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
 135                 fdt_setprop_string(fdt, offset, "phy-connection-type",
 136                                    "sgmii-2500");
 137                 fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
 138         }
 139 #endif
 140 }
 141
 142 void fdt_fixup_board_enet(void *fdt)
 143 {
 144 }