2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
9 #ifndef FSL_DDR_MEMCTL_H
10 #define FSL_DDR_MEMCTL_H
13 * Pick a basic DDR Technology.
17 #define SDRAM_TYPE_DDR1 2
18 #define SDRAM_TYPE_DDR2 3
19 #define SDRAM_TYPE_LPDDR1 6
20 #define SDRAM_TYPE_DDR3 7
22 #if defined(CONFIG_FSL_DDR1)
23 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
24 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
25 #ifndef CONFIG_FSL_SDRAM_TYPE
26 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
28 #elif defined(CONFIG_FSL_DDR2)
29 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
30 typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
31 #ifndef CONFIG_FSL_SDRAM_TYPE
32 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
34 #elif defined(CONFIG_FSL_DDR3)
35 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
36 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
37 #ifndef CONFIG_FSL_SDRAM_TYPE
38 #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
40 #endif /* #if defined(CONFIG_FSL_DDR1) */
42 /* define bank(chip select) interleaving mode */
43 #define FSL_DDR_CS0_CS1 0x40
44 #define FSL_DDR_CS2_CS3 0x20
45 #define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
46 #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
48 /* define memory controller interleaving mode */
49 #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
50 #define FSL_DDR_PAGE_INTERLEAVING 0x1
51 #define FSL_DDR_BANK_INTERLEAVING 0x2
52 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
54 /* Record of register values computed */
55 typedef struct fsl_ddr_cfg_regs_s {
59 unsigned int config_2;
60 } cs[CONFIG_CHIP_SELECTS_PER_CTRL];
61 unsigned int timing_cfg_3;
62 unsigned int timing_cfg_0;
63 unsigned int timing_cfg_1;
64 unsigned int timing_cfg_2;
65 unsigned int ddr_sdram_cfg;
66 unsigned int ddr_sdram_cfg_2;
67 unsigned int ddr_sdram_mode;
68 unsigned int ddr_sdram_mode_2;
69 unsigned int ddr_sdram_md_cntl;
70 unsigned int ddr_sdram_interval;
71 unsigned int ddr_data_init;
72 unsigned int ddr_sdram_clk_cntl;
73 unsigned int ddr_init_addr;
74 unsigned int ddr_init_ext_addr;
75 unsigned int timing_cfg_4;
76 unsigned int timing_cfg_5;
77 unsigned int ddr_zq_cntl;
78 unsigned int ddr_wrlvl_cntl;
79 unsigned int ddr_pd_cntl;
80 unsigned int ddr_sr_cntr;
81 unsigned int ddr_sdram_rcw_1;
82 unsigned int ddr_sdram_rcw_2;
85 typedef struct memctl_options_partial_s {
86 unsigned int all_DIMMs_ECC_capable;
87 unsigned int all_DIMMs_tCKmax_ps;
88 unsigned int all_DIMMs_burst_lengths_bitmask;
89 unsigned int all_DIMMs_registered;
90 unsigned int all_DIMMs_unbuffered;
91 /* unsigned int lowest_common_SPD_caslat; */
92 unsigned int all_DIMMs_minimum_tRCD_ps;
93 } memctl_options_partial_t;
96 * Generalized parameters for memory controller configuration,
97 * might be a little specific to the FSL memory controller
99 typedef struct memctl_options_s {
101 * Memory organization parameters
103 * if DIMM is present in the system
104 * where DIMMs are with respect to chip select
105 * where chip selects are with respect to memory boundaries
107 unsigned int registered_dimm_en; /* use registered DIMM support */
109 /* Options local to a Chip Select */
110 struct cs_local_opts_s {
111 unsigned int auto_precharge;
112 unsigned int odt_rd_cfg;
113 unsigned int odt_wr_cfg;
114 } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
116 /* Special configurations for chip select */
117 unsigned int memctl_interleaving;
118 unsigned int memctl_interleaving_mode;
119 unsigned int ba_intlv_ctl;
121 /* Operational mode parameters */
122 unsigned int ECC_mode; /* Use ECC? */
123 /* Initialize ECC using memory controller? */
124 unsigned int ECC_init_using_memctl;
125 unsigned int DQS_config; /* Use DQS? maybe only with DDR2? */
126 /* SREN - self-refresh during sleep */
127 unsigned int self_refresh_in_sleep;
128 unsigned int dynamic_power; /* DYN_PWR */
129 /* memory data width to use (16-bit, 32-bit, 64-bit) */
130 unsigned int data_bus_width;
131 unsigned int burst_length; /* 4, 8 */
133 /* Global Timing Parameters */
134 unsigned int cas_latency_override;
135 unsigned int cas_latency_override_value;
136 unsigned int use_derated_caslat;
137 unsigned int additive_latency_override;
138 unsigned int additive_latency_override_value;
140 unsigned int clk_adjust; /* */
141 unsigned int cpo_override;
142 unsigned int write_data_delay; /* DQS adjust */
143 unsigned int half_strength_driver_enable;
144 unsigned int twoT_en;
145 unsigned int threeT_en;
146 unsigned int bstopre;
147 unsigned int tCKE_clock_pulse_width_ps; /* tCKE */
148 unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */
150 /* Automatic self refresh */
151 unsigned int auto_self_refresh_en;
155 extern phys_size_t fsl_ddr_sdram(void);