2 * (C) Copyright 2007 DENX Software Engineering
4 * MPC512x Internal Memory Map
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * Based on the MPC83xx header.
24 #ifndef __IMMAP_512x__
25 #define __IMMAP_512x__
27 #include <asm/types.h>
29 typedef struct law512x {
30 u32 bar; /* Base Addr Register */
31 u32 ar; /* Attributes Register */
35 * System configuration registers
37 typedef struct sysconf512x {
38 u32 immrbar; /* Internal memory map base address register */
40 u32 lpbaw; /* LP Boot Access Window */
41 u32 lpcs0aw; /* LP CS0 Access Window */
42 u32 lpcs1aw; /* LP CS1 Access Window */
43 u32 lpcs2aw; /* LP CS2 Access Window */
44 u32 lpcs3aw; /* LP CS3 Access Window */
45 u32 lpcs4aw; /* LP CS4 Access Window */
46 u32 lpcs5aw; /* LP CS5 Access Window */
47 u32 lpcs6aw; /* LP CS6 Access Window */
48 u32 lpcs7aw; /* LP CS7 Access Window */
50 law512x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */
52 law512x_t ddrlaw; /* DDR Local Access Window */
54 u32 mbxbar; /* MBX Base Address */
55 u32 srambar; /* SRAM Base Address */
56 u32 nfcbar; /* NFC Base Address */
58 u32 spridr; /* System Part and Revision ID Register */
59 u32 spcr; /* System Priority Configuration Register */
64 * Watch Dog Timer (WDT) Registers
66 typedef struct wdt512x {
68 u32 swcrr; /* System watchdog control register */
69 u32 swcnr; /* System watchdog count register */
71 u16 swsrr; /* System watchdog service register */
76 * RTC Module Registers
78 typedef struct rtclk512x {
83 * General Purpose Timer
85 typedef struct gpt512x {
90 * Integrated Programmable Interrupt Controller
92 typedef struct ipic512x {
97 * System Arbiter Registers
99 typedef struct arbiter512x {
100 u32 acr; /* Arbiter Configuration Register */
101 u32 atr; /* Arbiter Timers Register */
102 u32 ater; /* Arbiter Transfer Error Register */
103 u32 aer; /* Arbiter Event Register */
104 u32 aidr; /* Arbiter Interrupt Definition Register */
105 u32 amr; /* Arbiter Mask Register */
106 u32 aeatr; /* Arbiter Event Attributes Register */
107 u32 aeadr; /* Arbiter Event Address Register */
108 u32 aerr; /* Arbiter Event Response Register */
115 typedef struct reset512x {
116 u32 rcwl; /* Reset Configuration Word Low Register */
117 u32 rcwh; /* Reset Configuration Word High Register */
119 u32 rsr; /* Reset Status Register */
120 u32 rmr; /* Reset Mode Register */
121 u32 rpr; /* Reset protection Register */
122 u32 rcr; /* Reset Control Register */
123 u32 rcer; /* Reset Control Enable Register */
130 typedef struct clk512x {
131 u32 spmr; /* System PLL Mode Register */
132 u32 sccr[2]; /* System Clock Control Registers */
133 u32 scfr[2]; /* System Clock Frequency Registers */
135 u32 bcr; /* Bread Crumb Register */
136 u32 pscccr[12]; /* PSC0-11 Clock Control Registers */
137 u32 spccr; /* SPDIF Clock Control Registers */
138 u32 cccr; /* CFM Clock Control Registers */
139 u32 dccr; /* DIU Clock Control Registers */
144 * Power Management Control Module
146 typedef struct pmc512x {
151 * General purpose I/O module
153 typedef struct gpio512x {
158 * DDR Memory Controller Memory Map
160 typedef struct ddr512x {
161 u32 ddr_sys_config; /* System Configuration Register */
162 u32 ddr_time_config0; /* Timing Configuration Register */
163 u32 ddr_time_config1; /* Timing Configuration Register */
164 u32 ddr_time_config2; /* Timing Configuration Register */
165 u32 ddr_command; /* Command Register */
166 u32 ddr_compact_command; /* Compact Command Register */
167 u32 self_refresh_cmd_0; /* Enter/Exit Self Refresh Registers */
168 u32 self_refresh_cmd_1; /* Enter/Exit Self Refresh Registers */
169 u32 self_refresh_cmd_2; /* Enter/Exit Self Refresh Registers */
170 u32 self_refresh_cmd_3; /* Enter/Exit Self Refresh Registers */
171 u32 self_refresh_cmd_4; /* Enter/Exit Self Refresh Registers */
172 u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */
173 u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */
174 u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */
175 u32 DQS_config_offset_count; /* DQS Config Offset Count */
176 u32 DQS_config_offset_time; /* DQS Config Offset Time */
177 u32 DQS_delay_status; /* DQS Delay Status */
179 u32 prioman_config1; /* Priority Manager Configuration */
180 u32 prioman_config2; /* Priority Manager Configuration */
181 u32 hiprio_config; /* High Priority Configuration */
182 u32 lut_table0_main_upper; /* LUT0 Main Upper */
183 u32 lut_table1_main_upper; /* LUT1 Main Upper */
184 u32 lut_table2_main_upper; /* LUT2 Main Upper */
185 u32 lut_table3_main_upper; /* LUT3 Main Upper */
186 u32 lut_table4_main_upper; /* LUT4 Main Upper */
187 u32 lut_table0_main_lower; /* LUT0 Main Lower */
188 u32 lut_table1_main_lower; /* LUT1 Main Lower */
189 u32 lut_table2_main_lower; /* LUT2 Main Lower */
190 u32 lut_table3_main_lower; /* LUT3 Main Lower */
191 u32 lut_table4_main_lower; /* LUT4 Main Lower */
192 u32 lut_table0_alternate_upper; /* LUT0 Alternate Upper */
193 u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */
194 u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */
195 u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */
196 u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */
197 u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */
198 u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */
199 u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */
200 u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */
201 u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */
202 u32 performance_monitor_config;
203 u32 event_time_counter;
204 u32 event_time_preset;
205 u32 performance_monitor1_address_low;
206 u32 performance_monitor2_address_low;
207 u32 performance_monitor1_address_hi;
208 u32 performance_monitor2_address_hi;
210 u32 performance_monitor1_read_counter;
211 u32 performance_monitor2_read_counter;
212 u32 performance_monitor1_write_counter;
213 u32 performance_monitor2_write_counter;
214 u32 granted_ack_counter0;
215 u32 granted_ack_counter1;
216 u32 granted_ack_counter2;
217 u32 granted_ack_counter3;
218 u32 granted_ack_counter4;
219 u32 cumulative_wait_counter0;
220 u32 cumulative_wait_counter1;
221 u32 cumulative_wait_counter2;
222 u32 cumulative_wait_counter3;
223 u32 cumulative_wait_counter4;
224 u32 summed_priority_counter0;
225 u32 summed_priority_counter1;
226 u32 summed_priority_counter2;
227 u32 summed_priority_counter3;
228 u32 summed_priority_counter4;
236 typedef struct dma512x {
241 * PCI Software Configuration Registers
243 typedef struct pciconf512x {
251 * PCI Outbound Translation Register
253 typedef struct pci_outbound_window {
265 typedef struct ios512x {
277 typedef struct pcictrl512x {
314 typedef struct mscan512x {
321 typedef struct bdlc512x {
328 typedef struct sdhc512x {
335 typedef struct spdif512x {
342 typedef struct i2c512x_dev {
343 volatile u32 madr; /* I2Cn + 0x00 */
344 volatile u32 mfdr; /* I2Cn + 0x04 */
345 volatile u32 mcr; /* I2Cn + 0x08 */
346 volatile u32 msr; /* I2Cn + 0x0C */
347 volatile u32 mdr; /* I2Cn + 0x10 */
351 typedef struct i2c512x {
352 i2c512x_dev_t dev[3];
361 typedef struct axe512x {
368 typedef struct diu512x {
375 typedef struct cfm512x {
382 typedef struct fec512x {
389 typedef struct ulpi512x {
396 typedef struct utmi512x {
403 typedef struct pcidma512x {
410 typedef struct ioctrl512x {
417 typedef struct iim512x {
418 u32 stat; /* IIM status register */
419 u32 statm; /* IIM status IRQ mask */
420 u32 err; /* IIM errors register */
421 u32 emask; /* IIM error IRQ mask */
422 u32 fctl; /* IIM fuse control register */
423 u32 ua; /* IIM upper address register */
424 u32 la; /* IIM lower address register */
425 u32 sdat; /* IIM explicit sense data */
427 u32 prg_p; /* IIM program protection register */
429 u32 divide; /* IIM divide factor register */
431 u32 fbac0; /* IIM fuse bank 0 prot (for Freescale use) */
432 u32 fb0w0[0x1f]; /* IIM fuse bank 0 data (for Freescale use) */
434 u32 fbac1; /* IIM fuse bank 1 protection */
435 u32 fb1w1[0x01f]; /* IIM fuse bank 1 data */
442 typedef struct lpc512x {
443 u32 cs_cfg[8]; /* Chip Select N Configuration Registers
444 No dedicated entry for CS Boot as == CS0 */
445 u32 cs_cr; /* Chip Select Control Register */
446 u32 cs_sr; /* Chip Select Status Register */
447 u32 cs_bcr; /* Chip Select Burst Control Register */
448 u32 cs_dccr; /* Chip Select Deadcycle Control Register */
449 u32 cs_hccr; /* Chip Select Holdcycle Control Register */
451 u32 sclpc_psr; /* SCLPC Packet Size Register */
452 u32 sclpc_sar; /* SCLPC Start Address Register */
453 u32 sclpc_cr; /* SCLPC Control Register */
454 u32 sclpc_er; /* SCLPC Enable Register */
455 u32 sclpc_nar; /* SCLPC NextAddress Register */
456 u32 sclpc_sr; /* SCLPC Status Register */
457 u32 sclpc_bdr; /* SCLPC Bytes Done Register */
458 u32 emb_scr; /* EMB Share Counter Register */
459 u32 emb_pcr; /* EMB Pause Control Register */
461 u32 lpc_fdwr; /* LPC RX/TX FIFO Data Word Register */
462 u32 lpc_fsr; /* LPC RX/TX FIFO Status Register */
463 u32 lpc_cr; /* LPC RX/TX FIFO Control Register */
464 u32 lpc_ar; /* LPC RX/TX FIFO Alarm Register */
471 typedef struct pata512x {
472 /* LOCAL Registers */
473 u32 pata_time1; /* Time register 1: PIO and tx timing parameter */
474 u32 pata_time2; /* Time register 2: PIO timing parameter */
475 u32 pata_time3; /* Time register 3: PIO and MDMA timing parameter */
476 u32 pata_time4; /* Time register 4: MDMA and UDMA timing parameter */
477 u32 pata_time5; /* Time register 5: UDMA timing parameter */
478 u32 pata_time6; /* Time register 6: UDMA timing parameter */
479 u32 pata_fifo_data32; /* 32bit wide dataport to/from FIFO */
480 u32 pata_fifo_data16; /* 16bit wide dataport to/from FIFO */
481 u32 pata_fifo_fill; /* FIFO filling in halfwords (READONLY)*/
482 u32 pata_ata_control; /* ATA Interface control register */
483 u32 pata_irq_pending; /* Interrupt pending register (READONLY) */
484 u32 pata_irq_enable; /* Interrupt enable register */
485 u32 pata_irq_clear; /* Interrupt clear register (WRITEONLY)*/
486 u32 pata_fifo_alarm; /* fifo alarm threshold */
488 /* DRIVE Registers */
489 u32 pata_drive_data; /* drive data register*/
490 u32 pata_drive_features;/* drive features register */
491 u32 pata_drive_sectcnt; /* drive sector count register */
492 u32 pata_drive_sectnum; /* drive sector number register */
493 u32 pata_drive_cyllow; /* drive cylinder low register */
494 u32 pata_drive_cylhigh; /* drive cylinder high register */
495 u32 pata_drive_dev_head;/* drive device head register */
496 u32 pata_drive_command; /* write = drive command, read = drive status reg */
498 u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */
505 typedef struct psc512x {
506 volatile u8 mode; /* PSC + 0x00 */
508 union { /* PSC + 0x04 */
510 volatile u16 clock_select;
512 #define psc_status sr_csr.status
513 #define psc_clock_select sr_csr.clock_select
515 volatile u8 command; /* PSC + 0x08 */
517 union { /* PSC + 0x0c */
518 volatile u8 buffer_8;
519 volatile u16 buffer_16;
520 volatile u32 buffer_32;
522 #define psc_buffer_8 buffer.buffer_8
523 #define psc_buffer_16 buffer.buffer_16
524 #define psc_buffer_32 buffer.buffer_32
525 union { /* PSC + 0x10 */
529 #define psc_ipcr ipcr_acr.ipcr
530 #define psc_acr ipcr_acr.acr
532 union { /* PSC + 0x14 */
536 #define psc_isr isr_imr.isr
537 #define psc_imr isr_imr.imr
539 volatile u8 ctur; /* PSC + 0x18 */
541 volatile u8 ctlr; /* PSC + 0x1c */
543 volatile u32 ccr; /* PSC + 0x20 */
544 volatile u8 res7[12];
545 volatile u8 ivr; /* PSC + 0x30 */
547 volatile u8 ip; /* PSC + 0x34 */
549 volatile u8 op1; /* PSC + 0x38 */
550 volatile u8 res10[3];
551 volatile u8 op0; /* PSC + 0x3c */
552 volatile u8 res11[3];
553 volatile u32 sicr; /* PSC + 0x40 */
554 volatile u8 res12[60];
555 volatile u32 tfcmd; /* PSC + 0x80 */
556 volatile u32 tfalarm; /* PSC + 0x84 */
557 volatile u32 tfstat; /* PSC + 0x88 */
558 volatile u32 tfintstat; /* PSC + 0x8C */
559 volatile u32 tfintmask; /* PSC + 0x90 */
560 volatile u32 tfcount; /* PSC + 0x94 */
561 volatile u16 tfwptr; /* PSC + 0x98 */
562 volatile u16 tfrptr; /* PSC + 0x9A */
563 volatile u32 tfsize; /* PSC + 0x9C */
564 volatile u8 res13[28];
565 union { /* PSC + 0xBC */
566 volatile u8 buffer_8;
567 volatile u16 buffer_16;
568 volatile u32 buffer_32;
570 #define tfdata_8 tfdata_buffer.buffer_8
571 #define tfdata_16 tfdata_buffer.buffer_16
572 #define tfdata_32 tfdata_buffer.buffer_32
574 volatile u32 rfcmd; /* PSC + 0xC0 */
575 volatile u32 rfalarm; /* PSC + 0xC4 */
576 volatile u32 rfstat; /* PSC + 0xC8 */
577 volatile u32 rfintstat; /* PSC + 0xCC */
578 volatile u32 rfintmask; /* PSC + 0xD0 */
579 volatile u32 rfcount; /* PSC + 0xD4 */
580 volatile u16 rfwptr; /* PSC + 0xD8 */
581 volatile u16 rfrptr; /* PSC + 0xDA */
582 volatile u32 rfsize; /* PSC + 0xDC */
583 volatile u8 res18[28];
584 union { /* PSC + 0xFC */
585 volatile u8 buffer_8;
586 volatile u16 buffer_16;
587 volatile u32 buffer_32;
589 #define rfdata_8 rfdata_buffer.buffer_8
590 #define rfdata_16 rfdata_buffer.buffer_16
591 #define rfdata_32 rfdata_buffer.buffer_32
597 typedef struct fifoc512x {
609 typedef struct sata512x {
613 typedef struct immap {
614 sysconf512x_t sysconf; /* System configuration */
616 wdt512x_t wdt; /* Watch Dog Timer (WDT) */
617 rtclk512x_t rtc; /* Real Time Clock Module */
618 gpt512x_t gpt; /* General Purpose Timer */
619 ipic512x_t ipic; /* Integrated Programmable Interrupt Controller */
620 arbiter512x_t arbiter; /* CSB Arbiter */
621 reset512x_t reset; /* Reset Module */
622 clk512x_t clk; /* Clock Module */
623 pmc512x_t pmc; /* Power Management Control Module */
624 gpio512x_t gpio; /* General purpose I/O module */
626 mscan512x_t mscan; /* MSCAN */
627 bdlc512x_t bdlc; /* BDLC */
628 sdhc512x_t sdhc; /* SDHC */
629 spdif512x_t spdif; /* SPDIF */
630 i2c512x_t i2c; /* I2C Controllers */
632 axe512x_t axe; /* AXE */
633 diu512x_t diu; /* Display Interface Unit */
634 cfm512x_t cfm; /* Clock Frequency Measurement */
636 fec512x_t fec; /* Fast Ethernet Controller */
637 ulpi512x_t ulpi; /* USB ULPI */
639 utmi512x_t utmi; /* USB UTMI */
641 pcidma512x_t pci_dma; /* PCI DMA */
642 pciconf512x_t pci_conf; /* PCI Configuration */
644 ios512x_t ios; /* PCI Sequencer */
645 pcictrl512x_t pci_ctrl; /* PCI Controller Control and Status */
647 ddr512x_t mddrc; /* Multi-port DDR Memory Controller */
648 ioctrl512x_t io_ctrl; /* IO Control */
649 iim512x_t iim; /* IC Identification module */
651 lpc512x_t lpc; /* LocalPlus Controller */
652 pata512x_t pata; /* Parallel ATA */
654 psc512x_t psc[12]; /* PSCs */
656 fifoc512x_t fifoc; /* FIFO Controller */
658 dma512x_t dma; /* DMA */
660 sata512x_t sata; /* Serial ATA */
663 #endif /* __IMMAP_512x__ */